List of Intel microprocessors

This list of Intel microprocessors attempts to present all of Intel's processors (µPs) from the pioneering 4-bit 4004 (1971) to the present high-end offerings, the 64-bit Itanium 2 (2002) and Pentium 4F with EM64T (2004). Concise technical data are given for each product.

Contents

1 The 4-bit and 8-bit processors 1.1 Intel 4004: 1st single-chip µP 1.2 4040 1.3 8008 1.4 8080 1.5 8085 2 The 16-bit processors: Origin of x86 2.1 8086 2.2 8088 2.3 80186 2.4 80188 2.5 80286 3 32-bit processors: The non-x86 µPs 3.1 iAPX 432 3.2 i960 aka 80960 3.3 i860 aka 80860 3.4 XScale 4 32-bit processors: The 80386 range 4.1 80386DX 4.2 80386SX 4.3 80376 4.4 80386SL 4.5 Intel386 EX 5 32-bit processors: The 80486 range 5.1 80486DX 5.2 80486SX 5.3 80486DX2 5.4 80486SL 5.5 80486DX4 6 32-bit processors: The Pentium ("I") 6.1 Pentium ("Classic") 6.2 Pentium MMX 7 32-bit processors: Pentium Pro, II, Celeron, III, M 7.1 Pentium Pro 7.2 Pentium II 7.3 Celeron (Pentium II-based) 7.4 Pentium III 7.5 Pentium II and III Xeon 7.6 Celeron (Pentium III Coppermine-based) 7.7 Celeron (Pentium III Tualatin-based) 7.8 Pentium M 7.9 Celeron M 8 32-bit processors: Pentium 4 range 8.1 Pentium 4 8.2 Xeon 8.3 Pentium 4EE 8.4 Pentium 4E 8.5 Pentium 4F 8.6 Pentium D 9 The 64-bit processors: Itanium & ... 9.1 Itanium 9.2 Itanium 2 9.3 EM64T 10 External links

The 4-bit and 8-bit processors

Intel 4004: 1st single-chip µP

• Introduced November 15, 1971
• Clock speed 740 kHz
• 0.06 MIPS
• Bus Width 4 bits (multiplexed address/data due to limited pins)
• PMOS
• Number of Transistors 2,300 at 10 μm
• Addressable Memory 640 bytes
• Program Memory 4K bytes
• World's first microprocessor
• Used in Busicom calculator
• Trivia: The original goal was to equal the clock speed of the IBM 1620; this was not quite met.

4040

• Introduced 4th Qtr, 1974
• Clock speed of 500 kHz to 740 kHz using 4 to 5.185 MHz crystals
• 0.06 MIPS
• Bus Width 4 bits (multiplexed address/data due to limited pins)
• PMOS
• Number of Transistors 3,000 at 10 μm
• Addressable Memory 640 bytes
• Program Memory 8K bytes
• Interrupts
• Enhanced version of 4004

8008

• Introduced April 1, 1972
• Clock speed 500 kHz (8008-1: 800 kHz)
• 0.05 MIPS
• Bus Width 8 bits (multiplexed address/data due to limited pins)
• PMOS
• Number of Transistors 3,500 at 10 μm
• Addressable memory 16 kilobytes
• Typical in dumb terminals, general calculators, bottling machines
• Developed in tandem with 4004
• Originally intended for use in the Datapoint 2200 terminal

8080

• Introduced April 1, 1974
• Clock speed 2MHz
• 0.64 MIPS
• Bus Width 8 bits data, 16 bits address
• NMOS
• Number of Transistors 6,000 at 6 μm
• Addressable memory 64 kilobytes
• 10X the performance of the 8008
• Used in the Altair 8800, Traffic light controller, cruise missile
• Required six support chips versus 20 for the 8008

8085

• Introduced March 1976
• Clock speed 5MHz
• 0.37 MIPS
• Bus Width 8 bits data, 16 bits address
• Number of Transistors 6,500 at 3 μm
• Used in Toledo scale
• High level of integration, operating for the first time on a single 5 volt power supply, from 12 volts previously

The 16-bit processors: Origin of x86

8086

• Introduced June 8, 1978
• Clock speeds:
  • 5MHz with 0.33 MIPS
  • 8MHz with 0.66MIPS
  • 10MHz with 0.75 MIPS
• Bus Width 16 bits data, 20 bits address
• Number of Transistors 29,000 at 3 μm
• Addressable memory 1 megabyte
• 10X the performance of 8080
• Used in portable computing
• Assembly language compatible with 8080
• Used segment registers to access more than 64K of data at once, bane of programmers' existence for years to come

8088

• Introduced June 1, 1979
• Clock speeds:
  • 5MHz with 0.33 MIPS
  • 8MHz with 0.75 MIPS
• Internal architecture 16 bits
• External bus Width 8 bits data, 20 bits address
• Number of Transistors 29,000 at 3 μm
• Addressable memory 1 megabyte
• Identical to 8086 except for its 8 bit external bus
• Used in IBM PCs and PC clones

iAPX 432 (chronological entry)

• Introduced January 1, 1981
• Multi-chip CPU; Intel's first 32-bit microprocessor
• See main entry

80186

• Introduced 1982
• Used mostly in embedded applications - controllers, point-of-sale systems, terminals, and the like
• Included two timers, a DMA controller, and an interrupt controller on the chip in addition to the processor
• Later renamed the iAPX 186

80188

• A version of the 80186 with an 8-bit external data bus
• Later renamed the iAPX 188

80286

• Introduced February 1, 1982
• Clock speeds:
  • 6MHz with 0.9 MIPS
  • 8MHz, 10MHz with 1.5 MIPS
  • 12.5MHz with 2.66 MIPS
• Bus Width 16 bits
• Included memory protection hardware to support multitasking operating systems with per-process address space
• Number of Transistors 134,000 at 1.5 μm
• Addressable memory 16 megabytes
• Added protected-mode features to 8086 with essentially the same instruction set
• 3-6X the performance of the 8086
• Widely used in PC clones at the time
• Can scan the Encyclopædia Britannica in 45 seconds

32-bit processors: The non-x86 µPs

iAPX 432

• Introduced January 1, 1981 as Intel's first 32-bit microprocessor
• Object/capability architecture
• Microcoded operating system primitives
• One terabyte virtual address space
• Hardware support for fault tolerance
• Two-chip General Data Processor (GDP), consists of 43201 and 43202
• 43203 Interface Processor (IP) interfaces to I/O subsystem
• 43204 Bus Interface Unit (BIU) simplifies building multiprocessor systems
• 43205 Memory Control Unit (MCU)
• Architecture and execution unit internal data paths 32 bit
• Clock speeds:
  • 5 MHz
  • 7 MHz
  • 8 MHz

80186, 80188, 80286, 80386(DX) (chronological entries)

• Introduced 1981–1988
• See main entries

i960 aka 80960

• Introduced April 5, 1988
• RISC-like 32-bit architecture
• predominantly used in embedded systems
• Evolved from the capability processor developed for the BiiN joint venture with Siemens
• Many variants identified by two-letter suffixes.

80386SX (chronological entry)

• Introduced June 16, 1988
• See main entry

80376 (chronological entry)

• Introduced January 16, 1989
• See main entry

i860 aka 80860

• Introduced February 27, 1989
• Intel's first superscalar processor
• RISC 32/64-bit architecture, with pipeline characteristics very visible to programmer
• Used in Intel Paragon massively parallel supercomputer

XScale

• Introduced August 23, 2000
• 32-bit RISC microprocessor based on the ARM architecture
• Many variants, such as the PXA2xx applications processors, IOP3xx I/O processors and IXP2xxx and IXP4xx network processors.

32-bit processors: The 80386 range

80386DX

• Introduced October 17, 1985
• Clock speeds:
  • 16MHz with 5 to 6 MIPS
  • 2/16/1987 20MHz with 6 to 7 MIPS
  • 4/4/1988 25MHz with 8.5 MIPS
  • 4/10/1989 33MHz with 11.4 MIPS (9.4 SPECint92 on Compaq/i 16K L2)
• Bus Width 32 bits
• Number of Transistors 275,000 at 1 μm
• Addressable memory 4 gigabytes
• Virtual memory 64 terabytes
• First x86 chip to handle 32-bit data sets
• Reworked and expanded memory protection support including paged virtual memory and virtual-86 mode, features required by Windows 95 and OS/2 Warp
• Used in Desktop computing
• Can address enough memory to manage an eight-page history of every person on earth
• Can scan the Encyclopædia Britannica in 12.5 seconds

80960 (i960) (chronological entry)

• Introduced April 5, 1988
• See main entry

80386SX

• Introduced June 16, 1988
• Clock speeds:
  • 16MHz with 2.5 MIPS
  • 1/25/1989 20MHz with 2.5 MIPS, 25MHz with 2.7 MIPS
  • 10/26/1992 33MHz with 2.9 MIPS
• Internal architecture 32 bits
• External bus width 16 bits
• Number of Transitors 275,000 at 1 μm
• Addressable memory 16 megabytes
• Virtual memory 256 gigabytes
• 16-bit address bus enable low cost 32-bit processing
• Built in multitasking
• Used in entry-level desktop and portable computing

80376

• Introduced January 16, 1989; Discontinued June 15, 2001
• Variant of 386 intended for embedded systems
• No "real mode", starts up directly in "protected mode"
• Replaced by much more successful 80386EX from 1994

80860 (i860) (chronological entry)

• Introduced February 27, 1989
• See main entry

80486DX (chronological entry)

• Introduced April 10, 1989
• See main entry

80386SL

• Introduced October 15, 1990
• Clock speeds:
  • 20MHz with 4.21 MIPS
  • 9/30/1991 25MHz with 5.3 MIPS
• Internal architecture 32 bits
• External bus width 16 bits
• Number of Transistors 855,000 at 1 μm
• Addressable memory 4 gigabytes
• Virtual memory 64 terabytes
• First chip specifically made for portable computers because of low power consumption of chip
• Highly integrated, includes cache, bus, and memory controllers

80486SX/DX2/SL, Pentium, 80486DX4 (chronological entries)

• Introduced 1991–1994
• See main entries

Intel386 EX

• Introduced August 1994
• Variant of 80386SX intended for embedded systems
• Static core, i.e. may run as slowly (and thus, power efficiently) as desired, down to full halt
• On-chip peripherals:
  • clock and power mgmt
  • timers/counters
  • watchdog timer
  • serial I/O units (sync and async) and parallel I/O
  • DMA
  • RAM refresh
  • JTAG test logic
• Significantly more successful than the 80376
• Used aboard several orbiting satellites and microsatellites
• Used in NASA's FlightLinux project

32-bit processors: The 80486 range

80486DX

• Introduced April 10, 1989
• Clock speeds:
  • 25MHz with 20 MIPS (16.8 SPECint92, 7.40 SPECfp92)
  • 5/7/1990 33MHz with 27 MIPS (22.4 SPECint92 on Micronics M4P 128k L2)
  • 6/24/1991 50MHz with 41 MIPS (33.4 SPECint92, 14.5 SPECfp92 on Compaq/50L 256K L2)
• Bus Width 32 bits
• Number of Transistors 1.2 million at 1 μm; the 50MHz was at 0.8 μm
• Addressable memory 4 gigabytes
• Virtual memory 64 terabytes
• Level 1 cache on chip
• 50X performance of the 8088
• Used in Desktop computing and servers

80386SL (chronological entry)

• Introduced October 15, 1990
• See main entry

80486SX

• Introduced April 22, 1991
• Clock speeds:
  • 9/16/1991 16MHz with 13 MIPS, 20MHz with 16.5 MIPS
  • 9/16/1991 25MHz with 20 MIPS (12 SPECint92)
  • 9/21/1992 33MHz with 27 MIPS (15.86 SPECint92)
• Bus Width 32 bits
• Number of Transistors 1.185 million at 1 μm and 900,000 at 0.8 μm
• Addressable memory 4 gigabytes
• Virtual memory 64 terabytes
• Identical in design to 486DX but without math coprocessor
• Used in low-cost entry to 486 CPU desktop computing
• Upgradable with the Intel OverDrive processor

80486DX2

• Introduced March 3, 1992
• Clock speeds:
  • 50MHz with 41 MIPS (29.9 SPECint92, 14.2 SPECfp92 on Micronics M4P 256K L2)
  • 8/10/1992 66 MHz with 54 MIPS (39.6 SPECint92, 18.8 SPECfp92 on Micronics M4P 256K L2)
• Bus Width 32 bits
• Number of Transistors 1.2 million at 0.8 μm
• Addressable memory 4 gigabytes
• Virtual memory 64 terabytes
• Used in high performance, low cost desktops
• Uses "speed doubler" technology where the microprocessor core runs at twice the speed of the bus

80486SL

• Introduced November 9, 1992
• Clock speeds:
  • 20MHz with 15.4MIPS
  • 25MHz with 19 MIPS
  • 33MHz with 25 MIPS
• Bus Width 32 bits
• Number of Transistors 1.4 million at 0.8 μm
• Addressable memory 64 megabytes
• Virtual memory 64 terabytes
• Used in notebook PCS

Pentium (chronological entry)

• Introduced March 22, 1993
• See main entry

80486DX4

• Introduced March 7, 1994
• Clock speeds:
  • 75MHz with 53 MIPS (41.3 SPECint92, 20.1 SPECfp92 on Micronics M4P 256K L2)
  • 100MHz with 70.7 MIPS (54.59 SPECint92, 26.91 SPECfp92 on Micronics M4P 256K L2)
• Number of Transistors 1.6 million at 0.6 μm
• Bus width 32 bits
• Addressable memory 4 gigabytes
• Virtual memory 64 terabytes
• Pin count 168 PGA Package, 208 SQFP Package
• Die size 345 Square mm
• Used in high performance entry-level desktops and value notebooks

32-bit processors: The Pentium ("I")

Pentium ("Classic")

• Introduced March 22, 1993
• P5 0.8 μm process technology
• Bus width 64 bits
• System bus speed 50 or 60 or 66 MHz
• Address bus 32 bits
• Number of transistors 3.1 million
• Addressable Memory 4 gigabytes
• Virtual Memory 64 terabytes
• Socket 4 273 pin PGA processor package
• Package dimensions 2.16" x 2.16"
• Superscalar architecture brought 5X the performance of the 33MHz 486DX processor
• Runs on 5 volts
• Used in desktops
• 16KB of L1 cache
• Variants
  • 60 MHz with 100 MIPS (70.4 SPECint92, 55.1 SPECfp92 on Xpress 256K L2)
  • 66 MHz with 112 MIPS (77.9 SPECint92, 63.6 SPECfp92 on Xpress 256K L2)
• P54C 0.6 μm process technology
• Socket 7 296/321 pin PGA package
• Number of transistors 3.2 million
  • 75 MHz Introduced October 10, 1994
  • 90 MHz Introduced March 7, 1994
  • 100 MHz Introduced March 7, 1994
  • 120 MHz Introduced March 27, 1995
• P54C 0.35 ²m process technology
• Number of transistors 3.3 million
• 90mm  die size
  • 120 MHz Introduced March, 1995
  • 133 MHz Introduced June, 1995
  • 150 MHz Introduced January 4, 1996
  • 166 MHz Introduced January 4, 1996
  • 200 MHz Introduced June 10, 1996

80486DX4 (chronological entry)

• Introduced March 7, 1994
• See main entry

80386EX (Intel386 EX) (chronological entry)

• Introduced August 1994
• See main entry

Pentium Pro (chronological entry)

• Introduced November 1995
• See main entry

Pentium MMX

• Introduced January 8, 1997
• P55C 0.35 μm process technology
• Intel MMX instructions
• Socket 7 296/321 pin PGA (pin grid array) package
• 32KB L1 cache
• Number of transistors 4.5 million
• System bus speed 66 MHz
• Variants
  • 166 MHz Introduced January 8, 1997
  • 200 MHz Introduced January 8, 1997
  • 233 MHz Introduced June 2, 1997
  • 166 MHz (Mobile) Introduced January 12, 1998
  • 200 MHz (Mobile) Introduced September 8, 1997
  • 233 MHz (Mobile) Introduced September 8, 1997
  • 266 MHz (Mobile) Introduced January 12, 1998
  • 300 MHz (Mobile) Introduced January 7, 1999

32-bit processors: Pentium Pro, II, Celeron, III, M

Pentium Pro

• Introduced November 1, 1995
• 0.6 μm process technology
• Precursor to Pentium II and III
• Socket 8 processor package (387 pins) (Dual SPGA)
• Number of transistors 22 million
• 16KB L1 cache
• 256KB integrated L2 cache
• 60 MHz system bus speed
• Variants
  • 150 MHz Introduced November 1, 1995
• 0.35 μm process technology, or 0.35 μm CPU with 0.6 μm L2 cache
• Introduced November 1, 1995
• Number of transistors 36.5 million or 22 million
• 512KB or 256KB integrated L2 cache
• 60 or 66 MHz system bus speed
• Variants
  • 166 MHz (66 MHz bus speed, 512KB 0.35 μm cache) Introduced November 1, 1995
  • 180 MHz (60 MHz bus speed, 256KB 0.6 μm cache) Introduced November 1, 1995
  • 200 MHz (66 MHz bus speed, 256KB 0.6 μm cache) Introduced November 1, 1995
  • 200 MHz (66 MHz bus speed, 512KB 0.35 μm cache) Introduced November 1, 1995
  • 200 MHz (66 MHz bus speed, 1MB 0.35 μm cache) Introduced August 18, 1997

Pentium II

• Introduced May 7, 1997
• Klamath 0.35 μm process technology (233, 266, 300MHz)
• Pentium Pro with MMX and improved 16-bit performance
• 242-pin Slot 1 (SEC) processor package
• Number of transistors 7.5 million
• 66MHz system bus speed
• 32KB L1 cache
• 512KB 1/2 speed external L2 cache
• Variants
  • 233 MHz Introduced May 7, 1997
  • 266 MHz Introduced May 7, 1997
  • 300 MHz Introduced May 7, 1997
• Deschutes 0.25 μm process technology (333, 250, 400, 450MHz)
• Introduced January 26, 1998
• 66MHz system bus speed (333MHz variant), 100MHz system bus speed for all models after
• Variants
  • 333 MHz Introduced January 26, 1998
  • 350 MHz Introduced April 15, 1998
  • 400 MHz Introduced April 15, 1998
  • 450 MHz Introduced August 24, 1998
  • 233 MHz (Mobile) Introduced April 2, 1998
  • 266 MHz (Mobile) Introduced April 2, 1998
  • 300 MHz (Mobile) Introduced September 9, 1998
  • 333 MHz (Mobile)

Celeron (Pentium II-based)

• Introduced April 15, 1998
• Covington - 0.25 μm process technology
• 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
• Number of transistors 7.5 million
• 66MHz system bus speed
• 32KB L1 cache
• No L2 cache
• Variants
  • 266 MHz Introduced April 15, 1998
  • 300 MHz Introduced June 9, 1998
• Mendocino - 0.25 μm process technology
• Introduced August 24, 1998
• 242-pin Slot 1 SEPP (Single Edge Processor Package), Socket 370 PPGA package
• Number of transistors 19 million
• 66MHz system bus speed
• 32KB L1 cache
• 128KB integrated cache
• Variants
  • 300A MHz Introduced August 24, 1998
  • 333 MHz Introduced August 24, 1998
  • 366 MHz Introduced January 4, 1999
  • 400 MHz Introduced January 4, 1999
  • 433 MHz Introduced March 22, 1999
  • 466 MHz
  • 500 MHz Introduced August 2, 1999
  • 533 MHz Introduced January 4, 2000
  • 266 MHz (Mobile)
  • 300 MHz (Mobile)
  • 333 MHz (Mobile) Introduced April 5, 1999
  • 366 MHz (Mobile)
  • 400 MHz (Mobile)
  • 433 MHz (Mobile)
  • 450 MHz (Mobile) Introduced February 14, 2000
  • 466 MHz (Mobile)
  • 500 MHz (Mobile) Introduced February 14, 2000

Pentium II Xeon chronological entry)

• Introduced June 29, 1998
• See main entry

Pentium III

• Introduced February 26, 1999
• Katmai - 0.25 μm process technology
• Improved PII, i.e. P6-based core, now including Streaming SIMD Extensions (SSE)
• Number of transistors 9.5 million
• 512KB 1/2 speed L2 External cache
• 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package
• System Bus Speed 100 MHz
• Variants
  • 450 MHz Introduced February 26, 1999
  • 500 MHz Introduced February 26, 1999
  • 550 MHz Introduced May 17, 1999
  • 600 MHz Introduced August 2, 1999
  • 533 MHz Introduced (133MHz bus speed) September 27, 1999
  • 600 MHz Introduced (133MHz bus speed) September 27, 1999
• Coppermine - 0.18 μm process technology
• Introduced October 25, 1999
• Number of transistors 28.1 million
• 256KB Advanced Transfer L2 Cache (Integrated)
• 242-pin Slot-1 SECC2 (Single Edge Contact cartridge 2) processor package, 370-pin FC-PGA (Flip-chip pin grid array) package
• System Bus Speed 100 MHz, 133 MHz (Those with 133 MHz bus carried a 'B' suffix in their name)
• Variants
  • 500 MHz (100MHz bus speed)
  • 533 MHz
  • 550 MHz (100MHz bus speed)
  • 600 MHz
  • 600 MHz (100MHz bus speed)
  • 650 MHz (100MHz bus speed) Introduced October 25, 1999
  • 667 MHz Introduced October 25, 1999
  • 700 MHz (100MHz bus speed) Introduced October 25, 1999
  • 733 MHz Introduced October 25, 1999
  • 750 MHz (100MHz bus speed) Introduced December 20, 1999
  • 800 MHz (100MHz bus speed) Introduced December 20, 1999
  • 800 MHz Introduced December 20, 1999
  • 850 MHz (100MHz bus speed) Introduced March 20, 2000
  • 866 MHz Introduced March 20, 2000
  • 933 MHz Introduced May 24, 2000
  • 1000 MHz Introduced March 8, 2000 (Not widely available at time of release)
  • 400 MHz (Mobile) Introduced October 25, 1999
  • 450 MHz (Mobile) Introduced October 25, 1999
  • 500 MHz (Mobile) Introduced October 25, 1999
  • 600 MHz (Mobile) Introduced January 18, 2000
  • 650 MHz (Mobile) Introduced January 18, 2000
  • 700 MHz (Mobile) Introduced April 24, 2000
  • 750 MHz (Mobile) Introduced June 19, 2000
  • 800 MHz (Mobile) Introduced September 25, 2000
  • 850 MHz (Mobile) Introduced September 25, 2000
  • 900 MHz (Mobile) Introducted March 19, 2001
  • 1000 MHz (Mobile) Introducted March 19, 2001
• Tualatin - 0.13 μm process technology
• Introduced July 2001
• Number of transistors 28.1 million
• 32KB L1 cache
• 256KB or 512KB Advanced Transfer L2 cache (Integrated)
• 370-pin FC-PGA (Flip-chip pin grid array) package
• 133 MHz system bus speed
• Variants
  • 1133 MHz (512KB L2)
  • 1200 MHz
  • 1266 MHz (512KB L2)
  • 1333 MHz
  • 1400 MHz (512KB L2)

Pentium II and III Xeon

• PII Xeon
• Variants
  • 400 MHz Introduced June 29, 1998
  • 450 MHz (512 KB L2 Cache) Introduced October 6, 1998
  • 450 MHz (1 MB and 2 MB L2 Cache) Introduced January 5, 1999
• PIII Xeon
• Introduced October 25, 1999
• Number of transistors: 9.5 million at 0.25 μm or 28 million at 0.18 μm)
• L2 cache is 256KB, 1MB, or 2MB Advanced Transfer Cache (Integrated)
• Processor Package Style is Single Edge Contact Cartridge (S.E.C.C.2) or SC330
• System Bus Speed 133 MHz (256KB L2 cache) or 100 MHz (1-2MB L2 cache)
• System Bus Width 64 bit
• Addressable memory 64 gigabytes
• Used in two-way servers and workstations (256KB L2) or 4- and 8-way servers (1-2MB L2)
• Variants
  • 500 MHz (0.25 μm process) Introduced March 17, 1999
  • 550 MHz (0.25 μm process) Introduced August 23, 1999
  • 600 MHz (0.18 μm process, 256KB L2 cache) Introduced October 25, 1999
  • 667 MHz (0.18 μm process, 256KB L2 cache) Introduced October 25, 1999
  • 733 MHz (0.18 μm process, 256KB L2 cache) Introduced October 25, 1999
  • 800 MHz (0.18 μm process, 256KB L2 cache) Introduced January 12, 2000
  • 866 MHz (0.18 μm process, 256KB L2 cache) Introduced April 10, 2000
  • 933 MHz (0.18 μm process, 256KB L2 cache)
  • 1000 MHz (0.18 μm process, 256KB L2 cache) Introduced August 22, 2000
  • 700 MHz (0.18 μm process, 1-2MB L2 cache) Introduced May 22, 2000

Celeron (Pentium III Coppermine-based)

• Introduced March,2000
• Coppermine-128 - 0.18 μm process technology
• Streaming SIMD Extensions (SSE)
• Socket 370 PPGA processor package
• Number of transistors 28.1 million
• 66MHz system bus speed, 100MHz system bus speed on January 3, 2001
• 32KB L1 cache
• 128KB Advanced Transfer L2 cache
• Variants
  • 533 MHz
  • 566 MHz
  • 633 MHz Introduced June 26, 2000
  • 667 MHz Introduced June 26, 2000
  • 700 MHz Introduced June 26, 2000
  • 733 MHz Introduced November 13, 2000
  • 766 MHz Introduced November 13, 2000
  • 800 MHz
  • 850 MHz Introducted April 9, 2001
  • 900 MHz Introducted July 2, 2001
  • 950 MHz Introduced August 31, 2001
  • 1000 MHz Introduced August 31, 2001
  • 1100 MHz Introduced August 31, 2001
  • 1200 MHz Introduced October 2, 2001
  • 1300 MHz Introduced January 3, 2002
  • 550 MHz (Mobile)
  • 600 MHz (Mobile) Introduced June 19, 2000
  • 650 MHz (Mobile) Introduced June 19, 2000
  • 700 MHz (Mobile) Introduced September 25, 2000
  • 750 MHz (Mobile) Introducted March 19, 2001
  • 800 MHz (Mobile)
  • 850 MHz (Mobile) Introduced July 2, 2001
  • 600 MHz (LV Mobile)
  • 500 MHz (ULV Mobile) Introducted January 30, 2001
  • 600 MHz (ULV Mobile)

XScale (chronological entry)

• Introduced August 23, 2000
• See main entry

Pentium 4 (not 4EE, 4E, 4F), Itanium, P4-based Xeon, Itanium 2 (chronological entries)

• Introduced April 2000 – July 2002
• See main entries

Celeron (Pentium III Tualatin-based)

• Tualatin Celeron - 0.13 μm process technology
• 32KB L1 cache
• 256KB Advanced Transfer L2 cache
• 100 MHz system bus speed
• Variants
  • 1.0 GHz
  • 1.1 GHz
  • 1.2 GHz
  • 1.3 GHz
  • 1.4 GHz

Pentium M

• Introduced March 2003
• Banias 0.13 μm process technology
• 64KB L1 cache
• 1MB L2 cache (integrated)
• Based on Pentium III core, with SIMD SSE2 instructions and deeper pipeline
• Number of transistors 77 million
• Micro-FCPGA, Micro-FCBGA processor package
• Heart of the Intel mobile "Centrino" system
• 400 MHz Netburst-style system bus.
• Variants
  • 900MHz (Ultra low voltage)
  • 1.0 GHz (Ultra low voltage)
  • 1.1 GHz (Low voltage)
  • 1.2 GHz (Low voltage)
  • 1.3 GHz
  • 1.4 GHz
  • 1.5 GHz
  • 1.6 GHz
  • 1.7 GHz
• Dothan 0.09 μm (90nm) process technology
• Introduced May 2004
• 2MB L2 cache
• Revised data prefetch unit
• Variants
  • 1.0 GHz (Ultra low voltage)
  • 1.1 GHz (Ultra low voltage)
  • 1.3 GHz (Low voltage)
  • 1.4 GHz (Low voltage)
  • 1.5 GHz
  • 1.6 GHz
  • 1.7 GHz
  • 1.8 GHz
  • 1.9 GHz
  • 2.0 GHz
  • 2.1 GHz
  • 2.2 GHz (To arrive in Q3 2005)
• Yonah 0.065 μm (65nm) process technology
• To be introduced 2006
• Dual Core variants with 2MB Shared L2 cache
• Variants
  • x20, x30, x40, x50, x38, x48 model numbers known

Celeron M

• Banias-512 0.13 μm process technology
• Introduced March 2003
• 64KB L1 cache
• 512KB L2 cache (integrated)
• No SpeedStep technology, is not part of the 'Centrino' package

32-bit processors: Pentium 4 range

Pentium 4

• 0.18 μm process technology (1.40 and 1.50 GHz)
  • Introduced November 20, 2000
  • L2 cache was 256KB Advanced Tansfer Cache (Integrated)
  • Processor Package Style was PGA423, PGA478
  • System Bus Speed 400 MHz
  • SSE2 SIMD Extensions
  • Number of Transistors 42 million
  • Used in desktops and entry-level workstations
• 0.18 μm process technology (1.7 GHz)
  • Introduced April 23, 2001
  • See the 1.4 and 1.5 chips for details
• 0.18 μm process technology (1.6 and 1.8 GHz)
  • Introduced July 2, 2001
  • See 1.4 and 1.5 chips for details
  • Core Voltage is 1.15 volts in Maximum Performance Mode; 1.05 volts in Battery Optimized Mode
  • Power <1 watt in Battery Optimized Mode
  • Used in full-size and then light mobile PCs
• 0.18 μm process technology "Willamette" (1.9 and 2.0 GHz)
  • Introduced August 27, 2001
  • See 1.4 and 1.5 chips for details
• Pentium 4 (2 GHz, 2.20 GHz)
  • Introduced January 7, 2002
• Pentium 4 (2.4 GHz)
  • Introduced April 2, 2002
• 0.13 μm process technology "Northwood A"(1.7, 1.8, 1.9, 2, 2.2, 2.4, 2.5, 2.6 GHz)
  • Improved branch prediction and other microcodes tweaks
  • 512KB integrated L2 cache
  • Number of transistors 55 million
  • 400 MHz system bus.
• 0.13 μm process technology "Northwood B" (2.26, 2.4, 2.53, 2.66, 2.8, 3.06 GHz)
  • 533 MHz system bus. (3.06 includes Intel's hyper threading technology).
• 0.13 μm process technology "Northwood C" (2.4, 2.6, 2.8, 3.0, 3.2, 3.4 GHz)
  • 800MHz system bus (all versions include Hyper Threading)
  • 6500 to 10000 MIPS

Itanium (chronological entry)

• Introduced 2001
• See main entry

Xeon

• Official designation now Xeon, i.e. not "Pentium 4 Xeon"
• Xeon 1.4, 1.5, 1.7 GHz
  • Introduced May 21, 2001
  • L2 cache was 256KB Advanced Transfer Cache (Integrated)
  • Processor Package Style was Organic Lan Grid Array 603 (OLGA 603)
  • System Bus Speed 400MHz
  • SSE2 SIMD Extensions
  • Used in high-performance and mid-range dual processor enabled workstations
• Xeon 2.0 GHz
  • Introduced September 25, 2001

Itanium 2 (chronological entry)

• Introduced July 2002
• See main entry

Pentium 4EE

• Introduced September 2003
• EE = "Extreme Edition"
• same as Pentium 4 Processor, but with 2MB onboard L3 Cache

Pentium 4E

• Introduced February 2004
• built on 0.09 μm (90 nm) process technology "Prescott" (2.4A, 2.8, 2.8A, 3.0, 3.2, 3.4, 3.6, 3.8) 1MB L2 cache
• 533MHz system bus (2.4A and 2.8A only)
• 800MHz system bus (all other models)
• Hyper-Threading support is only available on CPUs using the 800MHz system bus.
• The processor's integer instruction pipeline has been increased from 20 stages to 31 stages, which theoretically allows for even greater clock speeds.
• 7500 to 11000 MIPS
• LGA-775 versions are in the 5xx series (32-bit) and 5x1 series (with EM64T)
• The 6xx series has 2MB L2 cache and EM64T

Pentium 4F

• Introduced Spring 2004
• same core as 4E, "Prescott"
• 3.2–3.6 GHz
• starting with the D0 stepping of this processor, EM64T 64-bit extensions has also been incorporated

Pentium D

• Introduced Q2 2005
• "Smithfield" dual-core version
• 2.8–3.2 GHz
• 1MB+1MB L2 cache (non-shared, 2MB total)
• 800MHz system-bus
• Not hyperthreading, performance increase of 60% over similarly clocked Prescott
• Cache-coherency between cores requires communication over the 800MHz FSB

The 64-bit processors: Itanium & ...

Itanium

• Released May 29, 2001
• 733 MHz and 800 MHz

Itanium 2

• Released July 2002
• 900 MHz and 1 GHz

Pentium M (chronological entry)

• Introduced March 2003
• See main entry

Pentium 4EE, 4E (chronological entries)

• Introduced September 2003, February 2004, respectively
• See main entries

EM64T

• Intel® Extended Memory 64 Technology
• Introduced Spring 2004, with the Pentium 4F (D0 and later P4 steppings)
• 64-bit architecture extension for the x86 range; near clone of AMD64

External links

• The ChipList (http://www.chiplist.com/) – By Adrian Offerman
• Intel Museum: History of the Microprocessor (http://www.intel.com/intel/intelis/museum/online/hist_micro/hof/index.htm)bn:ইন্টেল মাইক্রোপ্রসেসরসমূহের তালিকা

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