ARM architecture

ARM's headquarters in
ARM's headquarters in Cambridge

The ARM architecture (originally the Acorn RISC Machine) is a 32-bit RISC processor architecture that is widely used in a number of applications. ARM variants are in widespread use in embedded and low-power applications due to their power saving design features.



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A Conexant ARM processor used mainly in routers

The ARM design was started in 1983 as a development project at Acorn Computers Ltd.

The team, led by Roger Wilson and Steve Furber, started development of what in some ways represents an advanced MOS Technology 6502. Acorn had a long line of computers based on the 6502, so a chip that was similar to program could represent a significant advantage for the company.

The team completed development samples called ARM1 by 1985, and the first "real" production systems as ARM2 the following year. The ARM2 featured a 32-bit data bus, a 26-bit address space and 16 32-bit registers. One of these registers served as the program counter with its top 6 bits holding the processor status flags. The ARM2 was possibly the simplest useful 32-bit microprocessor in the world, with only 30,000 transistors (compare with Motorola's four-year older 68000). Much of this simplicity comes from not having microcode (which represents about 1/4 to 1/3rd of the 68000) and (like most CPUs of the day) not including any cache. This simplicity leads to its excellent low-power needs, and yet it performed better than the 286. A successor, ARM3, was produced with a 4KB cache which further improved performance.

In the late 1980s Apple Computer started working with Acorn on newer versions of the ARM core. The work was so important that Acorn spun off the design team in 1990 into a new company called Advanced RISC Machines. For this reason you often see ARM lengthened to Advanced RISC Machine instead of Acorn RISC Machine. Advanced RISC Machines became ARM Limited when the company floated on the London Stock Exchange and NASDAQ in 1998.

This work would eventually turn into the ARM6. The first models were released in 1991, and Apple used the ARM6-based ARM 610 as the basis for their Apple Newton PDA.

The core has remained largely the same size throughout these changes. ARM2 had 30,000 transistors, while the ARM6 grew to only 35,000. The idea is that the end-user combines the ARM core with a number of optional parts to produce a complete CPU, one that can be built on old fabs and still deliver lots of performance at a low cost.

The most successful implementation has been the ARM7TDMI with hundreds of millions sold in cellular phones. While ARM's business has always been to sell IP-cores, some of the licenses generated microcontrollers based on this core.

DEC licensed the design (which caused some confusion because they also produced the DEC Alpha) and produced the StrongARM. At 233MHz this CPU drew only 1 watt of power (more recent versions draw far less). This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their aging i960 line with the StrongARM. Intel have since developed their own high performance implementation known by the name XScale.

Motorola, IBM, Texas Instruments, Nintendo, Philips, VLSI, Atmel, Sharp, Samsung and STMicroelectronics have also licensed the basic ARM design for various uses. The ARM chip has become one of the most used CPU designs in the world, found in everything from hard drives, to mobile phones, to routers, to calculators, to children's toys. Today it accounts for over 75% of all 32-bit embedded CPU's.

Design notes

The ARM instruction set follows the 6502 in concept, but includes a number of features designed to allow the CPU to better pipeline them for execution. In keeping with traditional RISC concepts, this included tuning the commands to execute in well-defined times, typically one cycle. A more interesting addition to the ARM design is the use of a 4-bit condition code on the front of every instruction, meaning that every instruction can be made a conditional.

This cuts down significantly on the space available for, for example, displacements in memory access instructions, but on the other hand it does make it possible to avoid branch instructions when generating code for small if statements. The standard example of this is Euclid's GCD algorithm:

(This example is in the C programming language)

int gcd(int i, int j) 
   while (i != j) 
      if (i > j) 
          i -= j;
          j -= i;
   return i;

Expressed in ARM assembly, the loop, with a little rotation, might look something like

       b test
loop   subgt  Ri,Ri,Rj
       suble  Rj,Rj,Ri
test   cmp    Ri,Rj
       bne    loop

which avoids the branches around the then and else clause that one would typically have to emit.

Another unique feature of the instruction set is the ability to fold shifts and rotates into the "data processing" (arithmetic, logical, and register-register move) instructions, so that, for example, the C statement "a += (j << 2);" could be rendered as a single instruction on the ARM, register allocation permitting.

This results in the typical ARM program being denser than what would normally be expected of a RISC processor. This implies that there is less need for load/store operations and that the pipeline is being used more efficiently. Even though the ARM runs at what many would consider to be low speeds, it nevertheless competes quite well with much more complex CPU designs.

The ARM processor also has some features rarely seen on other architectures that are considered RISC, such as PC-relative addressing (indeed, on the ARM the PC is one of its 16 registers) and pre- and post-increment addressing modes.

Another item of note is that the ARM has been around for a while, with the instruction set increasing somewhat over time. Some early ARM processors (prior to ARM7TDMI), for example, have no instruction to load a two-byte quantity, so that, strictly speaking, for them it's not possible to generate code that would behave the way one would expect for C objects of type "volatile short".


Perhaps in part because of the conditional execution facility using up four bits of every instruction, recent ARM processors have a 16-bit instruction mode, called Thumb. This is intended to allow smaller code where possible. As well as improving code density, performance can actually be higher than 32-bit code in situations where memory port or bus width are constrained to less than 32 bits. Typically in embedded applications a small range of addresses has a 32-bit datapath (e.g. the Game Boy Advance), and the rest is 16 bits wide or narrower; in this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using the 32-bit instruction set.

The first processor with Thumb technology was the ARM7TDMI. All ARM9 and later families, including XScale have included Thumb technology.


ARM have implemented a technology ( that allows certain of their architectures to execute Java bytecode natively in hardware, in another execution mode alongside the existing ARM and Thumb modes and accessed in a similar fashion to ARM/Thumb interworking.

The first processor with Jazelle technology was the ARM926EJ-S: Jazelle being denoted by the 'J' in the CPU name.


Thumb-2 technology made its debut in the ARM1156 core, announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth. As a result the stated aim for Thumb-2 is to achieve code density that is similar to Thumb with performance similar to the ARM instruction set on 32-bit memory.

Thumb-2 also extends both the ARM and Thumb instruction set with yet more instructions, including bit-field manipulation, table branches, and conditional execution.


NEON technology is a combined 64 and 128bit SIMD (Single Instruction Multiple Data) instruction set that provides standardized acceleration for media and signal processing applications. NEON can execute MP3 audio decoder in less than 10 CPU MHz and can run the GSM AMR (Adaptive Multi-Rate) speech codec using only 13 CPU MHz. It features a comprehensive instruction set, separate register files and independent execution hardware. NEON supports 8-, 16-, 32- and 64-bit integer and single precision floating-point data and operates in SIMD operations for handling audio/video processing as well as graphics and gaming processing. SIMD is a crucial element in vector supercomputers which feature simultaneous multiple operations. In NEON, the SIMD supports up to 16 operations at the same time.


VFP technology is a coprocessor extension to the ARM architecture. It provides low-cost single-precision and double-precision floating-point computation that is fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDA, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture also supports execution of short vector instructions allowing SIMD (Single Instruction Multiple Data) parallelism. This is useful in graphics and signal-processing applications by reducing code size and increasing throughput.

See also

External links

de:ARM-Architektur nl:ARM-instructieset pl:ARM fi:ARM fr:Processeur_ARM


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