IBM POWER

POWER is a RISC CPU architecture designed by IBM. The name stands for Performance Optimization With Enhanced RISC. The POWER series microprocessors are used as the main CPU in many of IBM's servers, minicomputers, workstations, and supercomputers. The POWER architecture was used to develop (and remains very similar to) the PowerPC architecture, used in later Apple Macintosh computers, some IBM workstations, as well as a number of embedded applications. IBM also is encouraging other developers and manufacturers to use the POWER architecture or any other derivative of it through the Power.org (http://www.Power.org/) community.

Contents

1 The architecture 2 Implementations 3 Derivative CPUs 4 External links

The architecture

The POWER design is descended directly from the earlier IBM 801 CPU, widely considered to be the first true RISC chip design. The 801 was used in a number of applications inside IBM hardware, but did not become publically known until they released the poorly-performing IBM PC/RT in the mid-1980s.

At about the same time the PC/RT was being released, IBM started the America Project, to design the most powerful CPU on the market. They were interested primarily in fixing two problems in the 801 design:

1. the 801 required all instructions to complete in one clock cycle, which eliminated floating point instructions
2. although the decoder was pipelined as a side effect of these single-cycle operations, they didn't use superscalar effects

Floating point became a focus for the America Project, and IBM was able to use new algorithms developed in the early 1980s that could support 64-bit double-precision multiplies and divides in a single cycle. The FPU portion of the design was separate from the instruction decoder and integer parts, allowing the decoder to send instructions to both the FPU and ALU (integer) execution units at the same time. IBM complemented this with a complex instruction decoder which could be fetching one instruction, decoding another, and sending one to the ALU and FPU at the same time, resulting in one of the first superscalar CPU designs in use.

The system used thirty-two 32-bit integer registers and another thirty-two 64-bit floating point registers, each in their own unit. The branch unit also included a number of "private" registers for its own use, including the program counter.

The 801 was a simple design, and an overcorrection to its simplicity resulted in the POWER design being more complex than most RISC CPUs. For instance, the POWER (and PowerPC) instruction set includes over 100 op-codes of variable length, many of which are variations on others. This compares (for instance) with the ARM which has only 34 instructions.

Another interesting feature of the architecture is a virtual address system which maps all addresses into a 52-bit space. In this way applications can share memory in a "flat" 32-bit space, and all of the programs can have different blocks of 32-bits each.

Implementations

The first POWER1 CPUs consisted of three chips; branch, integer and floating point. These were wired together on a largish motherboard to produce a single system. POWER1 was used primarily in the RS/6000 series of workstations.

POWER2 was a product-improved POWER1 and was the longest-lived of the POWER series, released in 1993 and still used five years later. It added a second floating-point unit, 256 kB of cache and 128-bit floating point math.

POWER3 followed in 1998, moving to a full 64-bit implementation, while remaining completely compatible with the POWER instruction set. This had been one of the goals of the PowerPC project and the POWER3 was the first of the IBM processors to take advantage of it. It also added a third ALU and a second instruction decoder, for a total of eight functional units.

The POWER4 series places two complete CPU cores (otherwise similar to the POWER3) on a single chip, speeds it up, and adds high-speed connections to up to three other pairs of POWER4 CPUs. They can be placed together on a motherboard to produce an 8-CPU SMP building block. When processing requires high throughput instead of high code complexity, one of a pair of cores can be turned off so that the remaining cores have the entire bus and L3 cache to themselves. The POWER4, even in single form, is considered by many to be the most powerful CPU available.

In 2003, IBM introduced a single CPU core version of the POWER4 called the 970. It was employed in the newest generation of Apple desktop computers (that is, the G5).

IBM rolled out the POWER5 processor in 2004. The 1.9 GHz version posted the highest uniprocessor SPECfp score of any shipping chip. The POWER5 powers the i5 and p5 eServers. Improvements in the POWER5 over the POWER4 include: a larger L2 cache, a memory controller on the chip, simultaneous multithreading which appears to the operating system as multiple CPUs, advanced power management, dedicated single-tasking mode, Hypervisor (virtualization technology), and eFuse (hardware re-routing around faults). Ravi Arimilli, IBM's chief microprocessor designer has said: "The POWER5 chip is more of a midrange design that can drive up to the high end and then down to things like blades." IBM servers build with POWER5 processor offer virtualization features: logical partitioning and micro partitioning. Up to ten LPARs (logical partitions) can be created for each CPU, the biggest 64-Way system can run 256 independent operating systems. Memory, CPU-Power and I/O can be dynamically moved between partitions. See also Linux on Power.

As of 2005, development of POWER6 and POWER7 variants is underway.

Derivative CPUs

The PowerPC was essentially a POWER1 CPU with some of the more basic instructions emulated in microcode, using a bus interface based on the Motorola 88000 design. This allowed IBM to use the CPU in a number of workstation machines, changing only the motherboard. Since then the PowerPC and POWER architectures have diverged somewhat, but remain compatible at the instruction level.

The IBM RS64 family of processors is based on PowerPC (and thus POWER) and has been used in the RS/6000 and AS/400 product lines. It is optimized for commercial workloads, and does not have the floating point power expected in the POWER line. It is now mostly replaced by the POWER4.

The Cell processor is also derived from the power architecture, resembling a POWER3-like core with limited floating point performance, coupled to eight independent vector processors. Intended to power the Sony PlayStation 3, the Cell appears to dramatically outperform almost all desktop processors on the market today, and has generated intense interest in the industry.

The Xbox 360, the next generation of Microsoft's gaming console will use a triple-core PowerPC processor clocked at 3.2 GHz[1] (http://www.xbox.com/en-US/xbox360/factsheet.htm).

External links

• IBM's Power Architecture page (http://www-1.ibm.com/technology/power/)
• Power.org (http://www.power.org/)
• When Is PowerPC Not PowerPC? (History of the POWER Architecture by Frank Soltis) (http://www.the400squadron.com/amug/200406/NotPowerPC.htm)de:IBM POWER

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