NMOS
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nMOS logic uses n-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. nMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active).
The n-type MOSFETs are arranged in a so-called "pull-down network" (PDN) between the output and low-voltage (ground) rail, while a resistor is placed between the output and the high-voltage rail. The circuit is designed such that if the desired output is low , then the PDN will be active, creating a current path between the low-voltage rail and the output.
As an example, here is a NOR gate in nMOS logic. If either input A or input B is high (logic 1, = True), the respective MOS transistor acts as a very low resistance between the output and the low-voltage supply rail, forcing the output to be low (logic 0, = False). When both A and B are high, both transistors are conductive, creating an even lower resistance path to ground. The only case where the output is high is when both transistors are off, which only occurs when both A and B are low, thus satisfying the truth table of a NOR gate:
| A | B | A NOR B |
|---|---|---|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
While nMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can literally be made with one type of component), it has several shortcomings as well. The worst problem is that a DC current flows through an nMOS gate when the PDN is active, that is whenever the output is low. This leads to static power dissipation even when the circuit sits idle.
Also, nMOS circuits are slow to transition from low to high. When transitioning from high to low, the transistors provide low resistance, and the capacitative charge at the output drains away very quickly. But the resistance between the output and the high supply rail is much greater, so the low to high transition takes longer. Using a resistor of lower value to speed up the process is a mixed blessing as this also increases power dissipation. Additionally, the asymmetric behaviour makes nMOS circuits susceptible to noise.
These disadvantages are why nMOS logic has been supplanted by CMOS both in low-power and in high-speed digital circuits, such as microprocessors, during the 1980s.de:nMOS