JHDL

From Academic Kids

JHDL is a hardware description language, implemented as a toolset and class library on top of the Java programming language, used for the design of FPGAs, primarily those from Xilinx. It natively supports outputing EDIF netlists for the XC4000, Virtex, and Virtex-II series of FPGAs.

JHDL features include, among other things, structural hardware design, flexible module generators, table-generated finite state machines, but it does not yet fully support behavioral synthesis. The integrated JHDL environment includes a graphical schematic viewer, a multiclock cycle-based simulator, and various other tools.

"JHDL" supposedly stands for Just-another Hardware Description Language, but because it is implemented in Java, it is supposed that is what inspired the J originally.

JHDL was developed at BYU in the Configurable Computing Laboratory.

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