Explicitly Parallel Instruction Computing
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Explicitly Parallel Instruction Computing (EPIC) is a computing paradigm that began to be researched in the 1990s. This paradigm is also called Independence architectures.
Due to the complexity of scaling the Out of Order execution and speculative execution paradigms, the processor industry in the mid-1990s started to re-examine instruction sets which explicitly encode multiple operations per instruction. The basis for such research is VLIW in which multiple operations for multiple functional units are encoded in every instruction. One goal is to move the complexity of dynamic scheduling of multiple instruction issue from the hardware implementation to the compiler, which can do the instruction scheduling statically (with help of trace feedback information). Another equally important goal is to further exploit instruction level parallelism (ILP).
VLIW (at least the original forms) has several short-comings that precluded it from becoming mainstream:
- Lack of instruction set backward compatibility between implementations. As wider implementations (more execution units) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.
- Load responses from a memory hierarchy which includes CPU caches and DRAM do not give a deterministic delay of when the load response returns to the processor. This makes static scheduling by the compiler of load instructions very difficult.
EPIC architectures add several features to get around these deficiencies:
- Each of the multiple operation instructions is called a bundle. Each of the bundles has information indicating if this set of operations is depended upon by the subsequent bundle. This allows future implementations to be built that can issue multiple bundles in parallel. The dependency information is calculated by the compiler, thus relieving the hardware implementation of doing operand dependency checking.
- A speculative load instruction is used as a type of data prefetch. This prefetch increases the chances for a primary cache hit for normal loads.
- A check load instruction that further aids speculative loads by checking that a load was not dependent on a previous store.
The EPIC architectures include a grab-bag of architectural concepts to increase ILP:
- predicated execution is used to decrease the occurrences of branches and increase the speculative execution of instructions. In this feature, branch conditions are converted to predicate registers which are used to kill results of executed instructions from the side of the branch which is not taken.
- Delayed exceptions (using a Not-A-Thing bit within the general purpose registers) also allow more speculative execution past possible exceptions.
- Very large architectural register file to avoid the need for register renaming.
- Multi-way branch instructions
The Itanium or IA64 architecture also added register rotation - a digital signal processing concept useful for loop un-rolling and software pipelining.
The Impact project at University of Illinois, led by Wen-mei Hwu has been the source of much influential research on this topic. The PlayDoh architecture from HP-labs is another major research project.
As of 2004, EPIC architectures have been successful in specific problem domains, specifically digital signal processors. They have been less successful in general purpose computing as it is debatable whether there is enough inherent instruction level parallelism in general purpose programs that these new features can exploit. Hewlett Packard, one of the progenitors of the Itanium architecture has announced that it has de-emphasized the architecture as of September, 2004.