A20 line

The A20 or addressing line 20 is one of the plethora of electrical lines which connect a microprocessor with memory and peripherals, and in particular allow to indicate which RAM locations it wants to read or write. A microprocessor will typically have a number of addressing lines equal to the base-two logarithm of its physical addressing space. For example an Intel 80386 with its 4 GB physical addressing space requires 32 lines, which are named A0 thru A31. The lines are named after the number of the bit in the address they are transmitting. Thus, A0 will transmit the least significant bit. A20 transmits bit number 20 and will become active once addresses reach 1MB or 220.

When IBM designed their IBM PC AT machine, they decided to use the new, higher-performance Intel 80286 microprocessor, which was not entirely compatible with the previous Intel 8088 and Intel 8086 microprocessors when running in compatibility real mode. On the old microprocessors, if software generated an address above 1MB (see High Memory Area for explanations about the method), this address would be implicitly wrapped around to 0, because the address space was limited to 1MB. The new chip could address up to 16MB and did not wrap around anymore.

In order to preserve compatibility of their new computers with existing software and leaving aside the possibility of asking Intel to make their chip more backwards compatible, IBM decided to fix the problem alone, at the motherboard level. To do this, they decided to simply allow disconnecting the addressing line A20 from the memory chips.

This was accomplished by inserting a logic gate on the A20 line, which logically got called Gate A20. Gate A20 could be set to passing or non-passing according to software needs; it would be set to non-passing for running old programs which relied on the wrap-around. At boot time, BIOS would first enable Gate A20 to be able to count and test the entire memory and would disable it when loading the operating system from diskette or hard disk.

Gate A20 was originally controlled through the keyboard controller of the mainboard. Later, more efficient methods have been added to allow better multitasking of programs which required the wrap-around with programs which wanted to access all memory.

It should be noted that disconnecting A20 would not wrap all memory accesses above 1MB, just those in the 1MB-2MB, 3MB-4MB, 5MB-6MB, etc. ranges. But real mode software only cared about the area slightly above 1MB, so Gate A20 was enough.

Over the time, the A20 line expression became confused with Gate A20 among less technically savvy audiences.

Enabling the A20 line is one of the first steps an operating system does in the bootup process, often before control has been passed onto the kernel from the bootstrap (in the case of Linux, for example).

With the arrival of Intel 80386, it became possible to simulate the wrap-around for virtual 8086 mode code by using the virtual memory facilities of the processor: physical memory pages mapped at virtual addresses from 0 till 64K can be simply mapped again starting from virtual address 1M onwards. The efficiency of Gate A20 toggling became irrelevant, as A20 will stay enabled all the time after the processor has entered protected mode. The operating system monitors Gate A20 requests issued by virtual machines and adapts the virtual memory map accordingly.

Starting with the Intel 80486, the manufacturer has added a special A20M# pin to its microprocessors. Pulling it low forces bit 20 of the physical address to be zero for all external bus memory accesses. This enhancement is however only significant for mainboard manufacturers, because it makes parts of the external Gate A20 circuitry unnecessary. Software still needs to manipulate the gate and must still deal with external peripherals (the chipset) for that.

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