Talk:VHSIC hardware description language
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Why say "program(me)"? Yes, I know opinions differ on which is correct. But the middle of a page about VHDL is not the right place to make that point.
There seems to be a movement towards "program" for computer instructions and "programme" for non-computer meanings.
Please decide which one is going to be used in Wikipedia and use it.
-- MartinPool
Misleading statement about VHDL
In the Discussion section the sentence `However, it is easy for the unwary and inexperienced to produce code that simulates successfully [...]' follows immediately the sentence `In this regard, it is considered by some to be superior to Verilog'. This could mislead the reader to think that the second sentence applies specifically to VHDL. In reality it applies to Verilog as well.
- I fixed this error. I assume that the flip-flop/latch pitfall doesn't apply to Verilog, but someone please tell me if I'm wrong. -- Heron 19:20, 14 Jul 2004 (UTC)
- Actually, the flip-flop/latch pitfall applies to Verilog as well.
I an new to Wikipedia, and I didn't see the discussion page before I edited the statement inder the VHDL discussion. The line I saw today seemed to imply that VHDL could do testbench work, and that verilog was less capable in this regard. In fact, both are very successful at these tasks, so I changed the sentence to reflect this. Gordwait
Hello World
I appreciate that the "Hello World" program is a tradition for languages but I don't really think it helps or adds anything to the article. I personally think that it just confuses matters as it doesn't really bear any relation to the way VHDL is used 99% of the time. Wouldn't it be better to replace it with an example of a simple testbench, or even something simple like a latch?
Another Example
library IEEE;
use IEEE.std_logic_1164.all;
entity Shifter is
port (
CLK : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC
);
end Shifter;
architecture behaviour of Shifter is
signal rShift : STD_LOGIC_VECTOR(3 downto 0);
begin
process(CLK)
begin
if CLK'event and CLK='1' then
rShift(3)<=D;
rShift(2 downto 0)<=rShift(3 downto 1);
end if;
end process;
Q <= rShift(0);
end behaviour;
Anyway: It is definitely possible to write "standard" programs in VHDL (for example a sorting algorithm). What I don't know if this "program"-orientated features of the language are actually used often. Where I work we don't use VHDL much for verification, but mostly for synthesis. Can anyone give a comment how widespread and how extensive VHDL is used for verfication ?
- I think this example is far more appropriate than the "hello world" example. - James Foster 11:31, 14 Jun 2005 (UTC)