IBM RS64
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The IBM RS64 family of processors is used in the RS/6000 and AS/400 server product lines. The family is optimized for commercial workloads (integer performance, large caches, branches) and does not feature the strong floating point performance of the IBM POWER family, its ancestor. It is a branch of the PowerPC family but includes special features not in the PowerPC specification and has been 64 bit from the start.
RS64 (Apache) was introduced in 1997 in the RS/6000 and AS/400 lines. It was developed from earlier PowerPC processors designed specifically for the AS/400. It featured 128 KB total on-die L1 cache, 4 MB full speed off-chip L2 on a 128 bit bus, and a clock of 125 MHz. It scaled to a 12 processor SMP configuration in IBM's machines.
RS64-II (Northstar) was introduced at 262 MHz in 1998 with 8 MB of full speed L2 on a 256 bit bus. Processor boards containing 4 RS64-II's could be swapped into machines designed for similar 4-way RS64 boards, avoiding a "fork lift upgrade".
RS64-III (Pulsar) was introduced in 1999 at 450 MHz with an 8 MB DDR SRAM L2 running at 450 MHz effective data rate on a 256 bit bus. On-chip L1 was increased to 256 KB total. Branch prediction was improved and branch misprediction penalty reduced to 0 or 1 cycles. It had a 5 stage pipeline and scaled to 24-way SMP.
RS64-IV (Istar, Sstar) was introduced in 2000 at 600 MHz, later increased to 750 MHz. Up to 16 MB DDR L2 was supported in the same manner as the RS64-III. It was the first mass-market processor to implement multithreading. Essentially, each chip stores state information for 2 threads at any given time and appears to be two processors to the OS. One logical processor runs what is called the foreground thread. When this thread encounters a high latency event (L2 cache miss, etc) the background thread is switched to, on the second logical processor from the OS's point of view. In the event of a "less long" latency event (L1 miss, etc), thread switching will only occur if the background thread is ready to execute. If the background thread is also waiting for a miss, thread switching will not occur. IBM calls this scheme "coarse grained multithreading". It is not exactly the same thing as simultaneous multithreading as found on later Pentium 4 processors. An IBM paper notes that the coarse grained scheme is a better fit for an in-order architecture like RS64. Unlike POWER, energy consumption remained low, at under 15 watts per core.
For a time, while the POWER line stagnated at half the clock speed of its competitors, the RS64 family was at the top of the IBM large SMP UNIX server line. The integer / commercial workload performance of the RS-64 IV was similar to the Sun Microsystems processors with which it competed, though its floating point power was not comparable to the contemporary POWER3-II, which remained reasonably competitive throughout its lifecycle. With the introduction of the POWER4, the RS64 family is being phased out.
External links
- IBM paper on RS64-IV (http://www.research.ibm.com/journal/rd/446/borkenhagen.html)
- 27 years of IBM RISC (http://www.rootvg.net/column_risc.htm)
- POWER to the people (http://www-106.ibm.com/developerworks/linux/library/l-powhist/)