Efficeon
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The Transmeta Efficeon processor is their second-generation 256-bit VLIW design which employs a software engine to convert code written for x86 processors to the native instruction set of the chip. Like its predecessor, the Transmeta Crusoe (a 128-bit VLIW architecture), Efficeon stresses computational efficiency, low power consumption, and a low thermal footprint.
Efficeon most closely mirrors the feature set of Intel Pentium 4 processor, although, like AMD Opteron processors, it supports a fully integrated memory controller, a Hypertransport IO bus and supports the NX bit, or no-execute, AMD64 x86 extension.
Efficeon's computational performance relative to mobile CPUs like the Intel Pentium M is thought to be lower, although little appears to be published about the relative performance of these competing processors.
Efficeon comes in two package types: a 783 and a 592 Ball Grid Array. Its power consumation is moderate (5 Watt at 1 GHz and 13 Watt at 1.3 GHz), so it can be passive cooled like the x386.
Internally, the Efficeon has 2 ALU Units, 2 Load/Store/Add Units, 2 Execute Units, 2 Floating point/MMX/SSE/SSE2 Units, one Branch Prediction Unit, one Alias and one Control Unit. This VLIW Processor can execute a 256 VLIW word per cycle, which is called a Molecule and therefore has room and capability to execute 8 32bit commands called Atoms per cycle.
The Efficeon has 128k + 64k Level 1 Cache and a 1Mb or 0.5Mb Level 2 Cache on chip. Additionally it has a Translation Cache for the dynamically translated x86 instructions by the Code morphing Software.
The Pentagon recently bought Notebooks with Transmeta chips because they consume less power and adapt power to the required tasks and further increase battery life.
External links
- Transmeta Efficeon Homepage (http://www.transmeta.com/efficeon/)de:Efficeon