VIA C3

The VIA C3 is an x86 central processing unit for personal computers. It is made by a Taiwanese company, VIA. Although the predecessor to the VIA C3 was called the "VIA Cyrix III," both it and the VIA C3 are based on the CPU design technology of Centaur Technology, makers of the WinChip C6. VIA bought Centaur from IDT.

As of March 2004 the fastest edition currently available works at the speed of 1.4 GHz with a 133 MHz front side bus on a Socket 370 motherboard or factory soldered EBGA on Mini-ITX mainboards. Both fanless and fan-cooled versions are available at 1GHz. Fan cooled versions are available at 1.3 GHz.

While being much slower than x86 CPUs being sold by AMD and Intel, both in absolute terms and on a clock for clock basis, VIA designed the chip for the low power segment of the market, and use simplicity in design, to deliver niche qualities which make it attractive to some buyers:

• The lowest manufacturing cost of all modern x86 processors by far, due to a mere 52 mm² die size on 0.13µ process. This compares to 84mm² for an Athlon XP, and 146mm² for a P4 Northwood. Due to wafer yields, manufacturing cost increases disproportionately with die size, so the P4 is actually rather more than 3 times more expensive to manufacture, on a like-for-like manufacturing process.
• Low electrical consumption levels, at only 11.25 watts maximum at 1GHz, or 20 watts at 1.3GHz. By comparison, the Pentium 4 consumes over 100 watts in higher clocked versions.
• Low heat output, enabling the processor to run under load either with a passive heatsink cooling solution, or a relatively small, quiet, and inexpensive fan.
• It runs on older Socket 370 motherboards, within a proprietary Enhanced Ball Grid Array (EBGA) package, that retains 370 features such as bus protocol and electrical interface. Available in BGA format for soldering directly to low cost boards

In some later (Nehemiah) versions it also features

• A high speed truly random hardware random number generator
• Very high performance AES encryption in hardware
• A BGA package the size of a 1 cent coin.

According to VIA, the VIA C3 was to be superseded in 2003 by the VIA C4 - a clone of the design of the Intel Pentium 4 processor. The VIA C4 naming was skipped because C4 is a high explosive. Instead VIA has released newer processors under the name C3 (also an explosive but less well known than C4) but with internal version names of C5B (Samuel2), C5C (Ezra), C5N (Ezra-T), C5XL (Nehemiah) and C5P (Nehemiah) all of which are still limited to 1.3Ghz, despite the VIA roadmap predicting 3Ghz by Q4 2003.

VIA C7

As of September 2004 VIA rationalised its naming scheme using the C3 naming for the earlier processors (Samuel, Samuel2, Ezra, Ezra-T, Nehemiah), C3-M for the mobile part ('Anataur') and C7/C7-M for upcoming 'Esther' processor cores. Versions of these processors also go under the name 'Eden' when they can be passively cooled and consume under 7W. The VIA C7 is a follow on to the VIA C3 line of processors and will start in first half 2005 with the release of the "Esther" core (known as C5J in some early announcements). The VIA C7 will add several features that are unique to this design

• Extending the hardware AES encryption support to include RSA
• SHA hash function support in hardware

It also seeks to end some of the fundamental problems with the older VIA C3 processor. In particular it supports a high speed front side bus, NX and SSE extensions. The VIA C7 will be manufactured by IBM on a 90nm silicon on insulator process, as speeds of up to 2 GHz.

VIA Design Methodology

AMD’s Athlon was optimised for processing power, with a highly sophisticated internal architecture, that has proved highly successful. The P4 was optimised for high clock speeds. However, VIA set size, power, and manufacturing cost as their primary design goals.

At the time of writing (2005), it is interesting to note that for the first time, thermal power is rapidly becoming the limit on processor performance. Intel has been unable to scale its next generation Prescott P4 to its intended operational frequencies >3.5 GHz, entirely due to thermal management issues.

So while VIA’s chips have always lacked performance, they are also not presently subject to thermal constraints on smaller manufacturing process technology. This enables VIA to continue to scale the frequencies of their chips, with each manufacturing process die shrink. To this extent, the performance gap that used to exist between VIA and competing x86 chips, is starting to narrow. Some of the design trade offs made by the VIA design team are worthy of study, as they ran contrary to accepted wisdom of the period.

• Because memory performance is the limiting factor in many benchmarks, the VIA chips implement large primary caches, large TLBs, aggressive prefetching, an efficient level-2 cache (new to the VIA C3 Samuel 2 and Ezra), among other enhancements. While these features are not unique to VIA, memory access optimization is one area, where they have not dropped features to save die space. In fact generous caches, especially primary, has always been a distinctive hallmark of Centaur / VIA designs.

• Clock frequency is in general terms favored over increasing instructions per cycle. Complex features such as out-of-order instruction execution are deliberately not implemented, because they impact MHz, require a lot of extra die space and power, and have little impact on performance in several common application scenarios. Internally, the C3 has 16 pipeline stages.

• The pipeline is arranged to provide one-clock execution of the heavily used register–memory and memory–register forms of x86 instructions. Many frequently used instructions require fewer pipeline clocks than on other x86 processors.

• Infrequently used x86 instructions are implemented in microcode and emulated. This saves die space and reduces power consumption. The impact upon the majority of real world application scenarios is minimized.

These design guidelines are startlingly reminiscent of those advocated by the original RISC advocates, who stated a smaller set of instructions, better optimized, would deliver faster overall CPU performance. We may therefore see RISC design values, having already heavily influenced development of the Athlon and Pentium 4 architectures, coming once again back into favor, as thermal considerations top out processor speed, and force design compromises, over brute force.

This is an especially interesting line of thought, when one considers the current trend towards multicore processors, exemplified most notably by IBM's 9 core Playstation 3 Cell processor. Given how much smaller and cooler the C7 is than rival parts, it might be possible to build a quad core C7, that cost the same to manufacture as a dual core Intel or AMD chip. The end result, would be more net processing power on a single die, than could be provided by hotter, larger, discrete cores.

External links

VIA C7 Processor (http://www.via.com.tw/en/products/processors/c7/)de:VIA C3