Translation Lookaside Buffer
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Translation Lookaside Buffers is a buffer (or cache) in a CPU that contains parts of the page table which references between virtual and real addresses. This buffer has a certain number of entries and is used for speed improvement. The buffer is typically a CAM (content addressable memory) in which the search key is the virtual address and the search result is a real or physical address (which, perversely, may not be the same thing). If the CAM search yields a match the translation is foregone and the match data are used. Otherwise, if no match exists the translation proceeds which will take several more cycles to complete - particularly if the translation tables are swapped out into secondary storage.
The TLB references physical memory addresses in its table. The TLB may reside between the CPU and the cache, or between the cache and primary storage. This depends on whether the cache is using virtual addressing or physical addressing.
If the cache is virtually addressed, requests are sent directly from the CPU to the cache, which then accesses the TLB as necessary. If the cache is physically addressed, the CPU does a TLB lookup on every memory operation, and the resulting physical address is sent to the cache. There are pros and cons to both implementations.
When a TLB miss occurs, the page table is checked to see if it has an entry for the specified virtual memory address. If it does, the address is brought into the TLB and requeried for (this can get complicated depending on whether it was a data or instruction TLB miss). If there is no entry in the page table, a page fault occurs. Template:Compu-hardware-stubde:Translation Lookaside Buffer