SSE2
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SSE2 is one of the IA-32 SIMD instruction sets, designed by Intel. It extends the earlier version SSE instruction set, and is intended to fully supplant MMX.
SSE2 adds support for 64-bit double-precision floating point and for 64, 32, 16 and 8-bit integer operations on the eight 128-bit XMM registers first introduced with SSE. SSE2 adds no additional program state to that provided by SSE.
The addition of 128-bit integer SIMD operations allows the programmer to completely avoid the eight 64-bit MMX registers "aliased" on the original IA-32 floating point registers. This permits mixing integer SIMD and scalar floating point operations without the time-consuming mode switching required in MMX and SSE.
Other SSE2 extensions include a set of cache-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information.
SSE2 was first introduced by Intel with the initial version of the Pentium 4 in 2001.
SSE2 has itself been extended by SSE3, also known as "Prescott New Instructions", introduced by Intel to the Pentium 4 in early 2004.
Rival chip-maker AMD later added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of 64-bit CPUs, in 2003. However, AMD extended SSE2 out beyond Intel's original implementation by doubling the number of XMM registers, from 8 to 16, i.e. XMM0 through XMM15. The additional registers are only visible when the processor is running in the 64-bit mode, known as AMD64. Intel also eventually adopted the additional XMM registers in 2004 along with the AMD64 (aka EM64T) architecture.de:Streaming SIMD Extensions 2 pl:SSE2