PowerPC

PowerPC is a RISC microprocessor architecture created by the 1991 Apple-IBM-Motorola alliance, known as AIM. Originally intended for workstations, PowerPC CPUs have since become popular embedded and high-performance processors as well. PowerPC was the cornerstone of AIM's PReP and Common Hardware Reference Platform initiatives in the 1990s, but the architecture found the most success in the personal computer market in Apple's Power Macintosh line from 1997 - 2005.

PowerPC is largely based on IBM's earlier (but retroactively named) POWER architecture, and retains a high level of compatibility with it; the architectures have remained close enough that the same programs and operating systems will run on both if some care is taken in preparation.

Contents

1 History 2 Design features 2.1 Endian-modes 3 Implementations and design wins 3.1 Design win summary 4 General-purpose PowerPC processors 5 Embedded PowerPC microcontrollers 5.1 IBM 5.2 Motorola (now Freescale Semiconductor) 6 References 7 External links

History

The history of the PowerPC begins with IBM's 801 prototype chip of John Cocke's RISC ideas in the late 70's. 801-based cores were used in a number of IBM embedded products, eventually becoming the 16-register ROMP processor used in the IBM RT. The RT had disappointing performance and IBM started the America Project to build the fastest processor on the market. The result was the POWER architecture, introduced with the RISC System/6000 in early 1990. It is noteworthy that this architecture was originally called "PowerPC" by IBM, the term "POWER" was coined several years later to differentiate between IBM's server-oriented processors and their desktop and embedded processors.

The original POWER microprocessor, one of the first superscalar RISC implementations, was a high performance, multi-chip design. IBM soon realized that they would need a single-chip microprocessor and to eliminate some POWER processor instructions to scale their RS/6000 line from lower-end to high-end machines, and work on a single-chip POWER microprocessor began. In early 1991 IBM realized that their design could potentially become a high-volume microprocessor used across the industry.

IBM approached Apple with the goal of collaborating on the development of a family of single-chip microprocessors based on the POWER architecture. Soon after, Apple, as one of Motorola's largest customers of desktop-class microprocessors, asked Motorola to join the discussions because of their long relationship, their more extensive experience with manufacturing high-volume microprocessors than IBM and to serve as a second source for the microprocessors. This three-way collaboration became known as AIM alliance, for Apple, IBM, Motorola.

To Motorola, POWER looked like an unbelievable deal. It allowed them to sell a widely tested and powerful RISC CPU for little design cash on their own part. It also maintained ties with an important customer, Apple, and seemed to offer the possibility of adding another in IBM who might buy smaller versions from them instead of making their own.

At this point Motorola already had its own RISC design in the form of the 88000 which was doing poorly in the market. One oft-quoted reason for its failure was the lack of backward compatibility with their own famous 68000 series, also used in the Apple Macintosh. A more likely reason was that the Motorola chips were consistently late to market due to poor design methodology and manufacturing issues, so late they lost their window of opportunity to be viable competitors to designs like the MIPS and SPARC which beat the 88000 to market.

However, the 88000 was already in production; Data General was shipping 88k machines and Apple already had 88k prototype machines running. If the new POWER single-chip solution could be made bus-comparable at a hardware level with the 88000, that would allow both Apple and Motorola to bring machines to market much faster since they would not have to redesign their board architecture.

The result of these various requirements was the PowerPC (Performance Computing) specification. Everyone seems to have won:

• IBM got the single-chip CPU they were looking for, largely for free
• Apple got to use one of the most powerful RISC CPU's on the market, and massive press buzz due to IBM's name
• Motorola got an up-to-date RISC chip for free, and help with design methodology from IBM

However, soon the same manufacturing issues began plaguing the AIM alliance in much the same way it did Motorola with consistently pushed back deployments of new processors for Apple and other vendors: first from Motorola in the 1990s with the G3 and G4 processors, and IBM with the 64-bit G5 processor in 2003. In 2004, Motorola exited the chip manufacturing business by spinning off its processor business to a company called Freescale Semiconductor. Around the same time, IBM exited the personal computer market completely by selling its line of PC products (which used Intel processors) to a Chinese company named Lenovo and focused their chip designs for PowerPC CPUs towards game machine makers such as Sony's Playstation 3 and Microsoft's Xbox 360. In 2005 Apple announced they would no longer use PowerPC processors in their Apple Macintosh computers, favoring Intel produced processors instead, citing the performance limitations of the chip for future personal computer hardware specifically related to heat generation and energy usage going forward, as well as the inability of IBM to move the 970 (PowerPC G5) processor to the 3 Ghz range. This was considered a public relations problem for IBM, since the decision was made in part by their inability to match Intel and other competitors in terms of speed and architecture improvements. This effectively ended the AIM alliance alliance with IBM continuing to use and evolve the PowerPC processor on game consoles and Freescale Semiconductor focusing soley on embedded devices.

This left the future of the PowerPC platform on anything other than embedded devices in much doubt. However, the original POWER architecture IBM developed and from which the PowerPC processor was originally derived was still very much alive on their server offerings for large businesses and continues to evolve to this day.

Design features

The PowerPC is designed along RISC principles, and allows for a superscalar implementation. Versions of the design exist in both 32-bit and 64-bit implementations. Starting with the basic POWER specification, the PowerPC added:

• Support for operation as in both Big-Endian and Little-Endian modes; the PowerPC can switch from one mode to the other at run-time (see below). This feature is not supported in the PowerPC G5. (This was the reason why Virtual PC took so long to be made functional on G5-based Macintoshes.)
• Single-precision forms of some floating point instructions, in addition to double-precision forms
• Additional floating point instructions at the behest of Apple
• A complete 64-bit specification, which is backward compatible with the 32-bit mode
• Removal of some of the more esoteric POWER instructions, some of which could be emulated by the operating system if necessary.

Endian-modes

In Little-Endian mode, the three lowest-order bits of the effective address are exclusive-ORed with a three bit value selected by the length of the operand. This is not quite the same as being truly little-endian, and can cause problems when communicating with external devices.

In theory the byte order of the processor can be switched at run-time to support both Big- and Little-Endian programs simultaneously, and in fact it is possible to run a program in one mode and exception handlers (in other words, the operating system) in another. Practically speaking this would be difficult due to the interaction with external devices which have their own byte ordering.

An interesting side-effect of this implementation is that a program can store a 64-bit value (the longest operand format) to an address A while in one endian mode, switch modes, and when the value is read back from A it will be identical, even though ostensibly the processor is now in the opposite byte order mode.

Implementations and design wins

The first single-chip implementation of the design was the MPC601, a hybrid of the POWER1 and PowerPC specifications released in 1992. This allowed the chip to be used by IBM in their existing POWER1 based platforms, although it also meant some slight pain when switching to the 2nd generation "pure" PowerPC designs. Apple continued work on a new line of Macintosh computers based on the chip, and eventually released them as the 601-based Power Macintosh on March 14, 1994.

IBM also had a full line of PowerPC based desktops built and ready to ship; unfortunately, the operating system which IBM had intended to run on these desktops—Microsoft Windows NT—was not complete by early 1993, when the machines were ready for marketing. Accordingly, and further because IBM had developed animosity toward Microsoft, IBM decided to rewrite OS/2 for the PowerPC. It took IBM two years to rewrite OS/2 for PowerPC, and by the time the operating system was ready, the market for OS/2 on PowerPC had evaporated. For this reason, the IBM PowerPC desktops did not ship, although the reference design (codenamed Sandalbow) based on the PowerPC 601 CPU was released as an RS/6000 model (Byte magazine 's April 1994 issue included an extensive article about the Apple and IBM PowerPC desktops).

Apple, who also lacked a PowerPC based OS, took a different route. They rewrote the essential pieces of their Mac OS operating system for the PowerPC architecture, and further wrote a 680x0 emulator which could run the remaining parts of the unrewritten OS and 68K based applications.

The second generation was "pure" and included the "low end" 603 and "high end" 604. The 603 is notable due to its very low cost and power consumption. This was a deliberate design goal on Motorola's part, who used the 603 project to build the basic core for all future generations of PPC chips. Apple tried to use the 603 in a new laptop design but was unable to due to the small 8KB level 1 cache. The 68000 emulator in the Mac OS could not fit in 8KB and thus slowed the computer drastically. The 603e solved this problem by having a 16KB L1 cache which allowed the emulator to run efficiently.

In 1993, developers at IBM's Burlington, Vermont facility started to work on a version of the PowerPC that would support the Intel x86 instruction set directly on the CPU. While the work was done by IBM without the support of the AIM alliance, this chip began to be known inside IBM and by the media as the PowerPC 615. However, profitability concerns and performance issues in the switching between the x86 and native PowerPC instruction sets resulted in the project being canceled in 1995 after only a limited number of chips were produced for in-house testing.[1] (http://www.theregister.co.uk/1998/10/01/microsoft_killed_the_powerpc/)

The first 64-bit implementation was the 620, but it appears to have seen little use since Apple didn't want to buy it and with its large die area, was too expensive for the embedded market. It was later and slower than promised, and IBM used their own POWER3 design instead, offering no 64-bit "small" solution until the late-2002 introduction of the PowerPC 970. The 970 is a 64-bit processor derived from the POWER4 server processor. To create it, the POWER4 core was modified to be backwards-compatible with 32-bit PowerPC processors, and a vector unit (similar to the AltiVec extensions in Motorola's 74xx series) was added.

IBM's RS64 family is a modified PowerPC architecture. These processors are used in the RS/6000 and AS/400 computer families.

Numerically, the PowerPC is mostly found in controllers in cars. In this role, Freescale Semiconductor has offered up a huge number of versions called the MPC5xx family such as the MPC555, built on a variant of the 601 core called the 8xx designed in Israel by MSIL (Motorola Silicon Israel Limited). The 601 core is single issue, meaning it can only issue one instruction in a clock cycle. To this they add various bits of custom hardware, to allow for I/O on the single chip.

Networking is another area where embedded PowerPC processors are found in large numbers. MSIL took the QUICC engine from the MC68302 and made the PowerQUICC MPC860. This was a very famous processor used in many Cisco edge routers in the late 1990s. Variants of the PowerQUICC include the MPC850, and the MPC823/MPC823e. All variants include a separate RISC microengine called the CPM that offloads communications processing tasks from the central processor and has functions for DMA. The follow-on chip from this family, the MPC8260, has a 603e-based core and a different CPM.

Design win summary

PowerPC processors have been used in many products, among which are the following: Apple Macintosh post-68k models (called PowerMacs), IBM RS/6000 UNIX workstations, Cisco routers, Pegasos (a Commodore Amiga spin off), Amiga acceleration boards, the Nintendo GameCube video game console, and many embedded systems such as the TiVo personal video recorder. Sonnet Technologies and Daystar manufacture PowerPC-based CPU upgrades for use in Macintosh systems. In 2003, NASA launched two Mars rovers (Spirit and Opportunity) that used PowerPC processors; essentially a harsh environment-resistant 604e.

All three of the major game console manufacturers have announced that their sixth-generation consoles will contain PowerPC-based processors:

• Sony's PlayStation 3 console, to be released in spring 2006, will contain a Cell processor, containing a 3.2 GHz PowerPC control processor, with eight 3.2 GHz closely-coupled DSP-like accelerator processors, seven active and one spare.
• Microsoft's Xbox 360 console, to be available from the 2005 holiday season, includes a 3.2 GHz custom IBM PowerPC chip with three symmetrical cores.
• The Nintendo Revolution console, predicted to ship some time in 2006, is billed as containing a PowerPC-based processor, but technical details have yet to be released.

General-purpose PowerPC processors

PowerPC processors bring the processor's local bus to the chip's surface, and connect to a bridge chip that translate this into other on-board device buses that attach to RAM, PCI, and other devices.

• 601 MPC601 50 and 66 MHz
• 602 consumer products (multiplexed data/address bus)
• 603 notebooks
• 603e
• 604
• 604e
• 620 the first 64-bit implementation
• x704 BiCOMOS PowerPC implementation by Exponential Technologies
• 750 (PowerPC G3) (1997) 233 MHz and 266 MHz, 740, 745, 755
• 7400 (PowerPC G4) (1999) 350 MHz, 7410 uses AltiVec, a SIMD extension of the original PPC specs
• 750FX announced by IBM in 2001 and available early 2002 at 1 GHz
• 7450 microarchitecture family
• 970 (PowerPC G5) (2003) A 64-bit implementation derived from the IBM POWER4 enhanced with VMX (AltiVec compatible SIMD extensions) operating at speeds of 1.4 GHz, 1.6 GHz, 1.8 GHz, 2.0 GHz, 2.3 GHz, 2.5 GHz and 2.7 GHz
• Gekko 485 MHz (used in the Nintendo GameCube)

Embedded PowerPC microcontrollers

32-bit PowerPC processors have been a favorite of embedded computer designers. To keep costs low on high-volume competitive products, the CPU core is usually bundled into a system-on-chip (SOC) integrated circuit. SOCs contain the processor core, cache and the processor's local data on-chip, along with clocking, timers, memory (SDRAM), peripheral (network, serial I/O), and bus (PCI, PCI-X, ROM/Flash bus, I2C) controllers. IBM and Motorola have competed along parallel development lines in overlapping markets. A recent development is the BookE PowerPC Specification, implemented by both IBM and Freescale Semiconductor, which defines embedded extensions to the PowerPC programming model.

IBM

• 401
• 403: MMU added in most advanced version 403GCX
• 405: MMU, ethernet, serial, PCI, SRAM, SDRAM; NPe405 adds more network devices
• 440GP: (BookE) MMU, multiple ethernet, serial, PCI-X, SRAM, SDRAM
• 440GX: adds more SRAM/L2 cache, TCP/IP acceleration hardware (TAH), gigabit ethernet MAC

Motorola (now Freescale Semiconductor)

• MPC 860 (PowerQUICC): User's Manual
• MPC 860/8xx (PowerQUICC): networking & telecomm card controllers
• MPC 550/5xx line: (8xx core) automotive & industrial controllers
• MPC 8260/82xx (PowerQUICC II) a 603 core, networking & telecomm system controllers with high-capacity onchip switched bus
• MPC 8560/85xx (PowerQUICC III) a BookE core, networking & telecomm system controllers with even higher-capacity onchip bus

References

• May, Cathy (editor) et.al. (1994). The PowerPC Architecture: A Specification for A New Family of RISC Processors. Morgan Kaufmann Publishers. ISBN 1-55860-316-6 (2nd ed.).
• Hoxey, Steve (editor) et.al. The PowerPC Compiler Writer's Guide. Warthman Associates. ISBN 0-9649654-0-2.
• Motorola. Programming Environments Manual for 32-bit Implementations of the PowerPC Architecture. P/N MPCFPE32B/AD .
• IBM (2000). Book E: Enhanced PowerPC™ Architecture (3rd ed.)
• Jeff Duntemann and Ron Pronk. (1994) Inside the PowerPC Revolution. Coriolis Group Books, ISBN 1-883577-04-7

External links

• A developer's guide to the PowerPC architecture (http://www-106.ibm.com/developerworks/linux/library/l-powarch/)– From IBM Developerworks.
• PowerPC road map at haxor.dk (http://haxor.dk/articles/ppc.html)
• PowerPC images and descriptions at cpu-collection.de (http://www.cpu-collection.de/?tn=1&l0=cl&l1=PowerPC)
• Like all Motorola processors, the PowerPC is produced by what was once Motorola's Semiconductor Products Sector, now spun off into an independent company named Freescale Semiconductor [2] (http://freescale.com/).
• Power.org (http://www.power.org) IBM's Power website
• OS/2 Warp, PowerPC Edition (http://pages.prodigy.net/michaln/history/os2ppc/index.html) review by Michael Necasek 2005
• PearPC (http://pearpc.sourceforge.net) - PowerPC architecture emulator

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