PCI Express
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PCI Express (formerly known as 3GIO for 3rd Generation I/O, not to be mistaken with PCI-X) is an implementation of the PCI computer bus that uses existing PCI programming concepts and communications standards, but bases it on a much faster serial communications system. It is being supported primarily by Intel, who started working on the standard as the Arapahoe project after pulling out of the InfiniBand system.
PCI Express is intended to be used as a local bus only. Due to it being based on the existing PCI system, cards and systems can be converted to PCI Express by changing the physical layer only – existing systems could be re-booted on PCI Express and never even know it. The higher speeds on PCI Express allow it to replace almost all existing internal buses, including AGP and PCI, and Intel envisions a single PCI Express controller talking to all external devices, as opposed to the northbridge/southbridge solution in current machines.
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Specification
The full specification for PCI Express and all other PCI specifications are published and controlled by PCI-SIG (PCI Special Interest Group).
Hardware protocol summary
A connection between any two PCI Express devices is known as a "Link". All devices must minimally support single-lane (x1) links. Devices may optionally support wider links composed of 2, 4, 8, 12, 16, or 32 "Lanes".
At the electrical level, each Lane utilizes two unidirectional low voltage differential signaling (LVDS) pairs at 2.5 gigabit/s. (Transmit and receive are separate diff-pairs.)
Data transmitted on multiple lane links is interleaved, meaning that each successive byte is sent down successive lanes. The PCI Express specification refers to this interleaving as "data striping". While requiring significant hardware complexity to synchronize (or deskew) the incoming striped data, striping can significantly increase the data-throughput of the link. (Due to packet protocol rules, striping may not necessarily reduce the latency of small data packets on a link.)
As with all high-speed serial transmission protocols, clocking information must be embedded in the signal. At the physical level, PCI Express utilizes the very common 8B/10B encoding scheme to ensure that long strings of ones or zeros are broken up enough that the receiver doesn't lose track of where the bit edges are. This coding scheme replaces 8 uncoded (payload) bits of data with 10 (encoded) bits of transmitted data, consuming 20% of the overall electrical bandwidth.
Some other protocols (such as SONET) use a different form of encoding known as "scrambling" to embed clock information into data streams. The PCI Express specification also defines a scrambling algorithm, but its form of scrambling is not to be confused with the scrambling included in SONET. Rather than embedding clock information, the scrambling in PCI Express is designed to prevent repeating data patterns in the transmitted data stream from causing RF emission peaks.
First-generation PCIe is constrained to a single signalling-rate of 2.5 Gigabits/s. PCI-SIG plans future versions adding signalling rates of 5 and 10 Gigabit/s.
First-generation PCIe is often quoted to support a data-rate of 250 MB/s in each direction, per each lane. This figure is a calculation from the physical signalling-rate (2500 Mbit/s) divided by the encoding overhead (10bits/byte.) This means a 16 lane (x16) PCIe card would then be theoretically capable of 250 * 16 = 4000 MB/s in each direction. The truth is that the usable data-payload rate depends on the profile of the traffic, which is a function of the high-level (software) application.
Like other high-speed serial interconnect systems, PCIe has significant protocol and processing overhead. Long continuous unidirectional transfers (such as those typical in high-performance storage controllers) can approach >95% of PCIe's raw (channel) data-rate. These transfers also benefit the most from increased number of lanes (x2, x4, etc.) But in more typical applications (such as a USB or ethernet controller), the traffic profile is characterized as short data-packets with frequent enforced acknowledgements. This type of traffic reduces the efficiency of the link, due to overhead from packet-parsing and forced-interrupts (either in the device's host-interface or the PC's CPU.) This is by no means a criticism of the PCIe specification -- merely a reminder that PCIe is not exempt to the rules of a layered packet protocol, no more so than other comparable high-speed serial technologies (such as SerialATA and Fibre Channel).
Form factors
The following form factors have been specified for PCI Express devices:
- Regular card
- Low height card
- Mini Card: a replacement for the Mini PCI form factor (with x1 PCIe, USB 2.0 and SMBus buses on the connector)
- ExpressCard: similar to the PCMCIA form factor, (with x1 PCIe and USB 2.0; hot-pluggable)
- AdvancedTCA: a replacement for CompactPCI
Competing protocols
Several communications standards have emerged based on high speed serial architectures. These include but are not limited to HyperTransport, InfiniBand, RapidIO, and StarFabric. There are industry proponents of each, and since significant funds have been invested in their development, each consortium tends to emphasize the advantages of its variant over others.
Essentially the differences are based on the tradeoffs between flexibility and extensibility vs. latency and overhead. An example of such a tradeoff is adding complex header information to a transmitted packet to allow for complex routing (PCI Express is not capable of this). This additional overhead reduces the effective bandwidth of the interface and complicates bus discovery and initialization software. Also making the system hot-pluggable requires that software track network topology changes. Examples of busses suited for this purpose are InfiniBand and StarFabric.
Another example is making the packets shorter to decrease latency (as is required if a bus is to be operated as a memory interface). Smaller packets mean that the packet headers consume a higher percentage of the packet, thus decreasing the effective bandwidth. Examples of bus protocols designed for this purpose are RapidIO and HyperTransport.
PCI Express falls somewhere in the middle, targeted by design as a system interconnect (local bus) rather than a device interconnect or routed network protocol. Additionally, its design goal of software transparency constrains the protocol and raises its latency somewhat.
Outlook
PCI Express appears, as of 2004, to be well on its way to becoming the new backplane standard in personal computers. There are several explanations for this, but the two principal reasons are that it has strong brand recognition and that it was designed to be completely transparent to software developers (an operating system designed for PCI can boot in a PCI Express system without any code modification).
High-end graphics cards from both ATI Technologies and nVidia have recently been converted from AGP to PCI Express, which may be the incentive needed for other companies and devices to follow suit. PCI Express has now also started appearing on Athlon 64 based systems where previously it was exclusive to Intel based ones.
External links
- PCI Special Interest Group (http://www.pcisig.com/home)
- PCI Express Specifications and White Papers (http://www.pcisig.com/specifications/pciexpress/)
- Creating a Third Generation I/O Interconnect (PDF) (http://developer.intel.com/technology/pciexpress/downloads/3rdGenWhitePaper.pdf)
- Intel Developer Network for PCI Express Architecture (http://www.intel.com/technology/pciexpress/devnet/)
- Ars Technica introduction to PCI Express (http://arstechnica.com/paedia/p/pci-express/pcie-1.html)cs:PCI-Express
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