Memory barrier
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Memory barrier, also known as membar or memory fence is a name for a class of instructions for a computer in computer architecture.
In order to improve performance, modern CPUs employ mechanisms which can result in operations being executed out-of-order, including memory loads and stores. The reordering of memory operations is done in such a way that it is not normally noticeable within a single thread of execution, but it can result in unpredictable behaviour in concurrent programs and device drivers unless it is carefully controlled. A memory barrier is a general term used to refer to instructions which cause the CPU to enforce an ordering constraint on memory operations issued before and after the barrier instruction. The exact nature of the ordering constraint is hardware dependent, and is defined by the architecture's memory model. Some architectures provide multiple barriers for enforcing different ordering constraints.
Memory barriers are typically used when implementing low-level code, which operates on memory shared by multiple devices. Such code includes synchronization primitives and lock-free data structures on multiprocessor systems, and device drivers which communicate with hardware.
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An Illustrative Example
When a program runs on a single CPU, the hardware performs the necessary book-keeping to ensure that programs execute as if all memory operations were performed in program order, hence memory barriers are not necessary. However, when the memory is shared with multiple devices, such as other CPUs in a multiprocessor system, or memory mapped peripherals, out-of-order access may affect program behavior. For example a second CPU may see memory changes made by the first CPU in a sequence which differs from program order.
The following two processor program gives a concrete example of how such out-of-order execution can affect program behavior:
Initially, memory locations x and f both hold the value 0. The program running on processor #1 loops until the value of f is non-zero, then it prints the value of x. The program running on processor #2 stores the value 42 into x and then stores the value 1 into f. Pseudo code for the two program fragments is shown below. The steps of the program correspond to individual processor instructions. Processor #1: loop: load the value in location f, if it is 0 goto loop print the value in location x Processor #2: store the value 42 into location x store the value 1 into location f
You might expect the print statement to always print the number "42", however if processor #2's store operations are executed out-of-order it is possible that f would be updated before x, and the print statement might print "0". For most programs this situation is not acceptable. A memory barrier can be inserted before processor #2's assignment to f to ensure that the new value of x was visible to other processors at or prior to the change in the value of f.
Low Level Architecture-Specific Primitives
Memory barriers are low level primitives which are part of the definition of an architecture's memory model. Like instruction sets, memory models vary considerably between architectures, so it is not appropriate to generalise about memory barrier behavior. The received wisdom is that to use memory barriers correctly you should study the architecture manuals for the hardware which you are programming. That said, the following paragraph offers a glimpse of some memory barriers which exist in the wild.
Some architectures provide only a single memory barrier instruction sometimes called "full fence". A full fence ensures that all load and store operations prior to the fence will have been committed prior to any loads and stores issued following the fence. Other architectures provide separate "acquire" and "release" memory barriers which address the visibility of read-after-write operations from the point of view of a reader (sink) or writer (source) respectively. Some architectures provide separate memory barriers to control ordering between different combinations of system memory and I/O memory. When more than one memory barrier instruction is available it is important to consider that the cost of different instructions may vary considerably.
"Threaded" Programming and Memory Visibility
Threaded programs usually use synchronisation primitives provided by a high-level programming environment such as Java, or a API such as POSIX pthreads or Win32. Primitives such as mutexes and semaphores are provided to synchronize access to resources from parallel threads of execution. These primitives are usually implemented with the memory barriers required to provide the expected memory visibility semantics. When using such environments explicit use of memory barriers is not generally necessary.
Each API or programming environment in principle has its own high-level memory model that defines its memory visibility semantics. Although you do not usually need to use memory barriers in such high level environments, it is important to understand their memory visibility semantics, to the extent possible. Such understanding is not necessarily easy to achieve because memory visibility semantics are not always consistently specified or documented.
Just as programming language semantics are defined at a different level of abstraction to machine language opcodes, a programming environment's memory model is defined at a different level of abstraction to that of a hardware memory model. It is important to understand this distinction and realise that there is not always a simple mapping between low-level hardware memory barrier semantics and the high-level memory visibility semantics of a particular programming environment. As a result, a particular platform's implementation of (say) pthreads may employ stronger barriers than required by the specification. Programs which take advantage of memory visibility as-implemented rather than as-specified may not be portable.
Out-of-order Execution vs. Compiler Reordering Optimisations
Memory barrier instructions only address reordering effects at the hardware level. Compilers may also reorder instructions as part of the program optimization process. Although the effects on parallel program behavior can be similar in both cases, in general it is necessary to take separate measures to inhibit compiler reordering optimisations for data that may be shared by multiple threads of execution. Note that such measures are usually only necessary for data which is not protected by synchronisation primitives such as those discussed in the previous section.
In C, the volatile keyword is provided to inhibit optimisations which remove or reorder memory operations on a variable marked as volatile. This will provide a kind of barrier for interruptions which occur on a single CPU, such as signal handlers or concurrent threads on a uniprocessor system. However, the use of volatile is insufficient to guarantee correct ordering for multiprocessor systems because it only impacts reorderings performed by the compiler, not those which may occur at runtime such as those performed by the CPU.
Some languages and compilers may provide sufficient facilities to implement functions which address both the compiler reordering and machine reordering issues, however it is usually advisable to be very careful about this, for example by carefully inspecting compiler generated code. Some developers advocate coding in assembly language to avoid compiler reordering issues.
See also
External links
- Microsoft Driver Development: Memory Barriers on Multiprocessor Architectures (http://www.microsoft.com/whdc/driver/kernel/MPmem-barrier.mspx)
- HP technical report HPL-2004-209: Threads Cannot be Implemented as a Library (http://www.hpl.hp.com/techreports/2004/HPL-2004-209.html)
- OldNewThing Blog on the subject (http://weblogs.asp.net/oldnewthing/archive/2004/05/28/143769.aspx)