LARC

The UNIVAC LARC (Livermore Advanced Research Computer) was Remington Rand's first attempt at building a supercomputer. It was designed for multiprocessing with 2 CPUs (called Computers) and an I/O Processor (called the Processor).

Only two LARCs were built:

1. The first was delivered to Livermore in June 1960.
2. The second was delivered to the Navy's David Taylor Model Basin.

The LARC was a mainframe computer with 48 bits per word. It used bi-quinary coded decimal arithmetic with 4 bits per digit, allowing 11 digit signed numbers. Instructions were 48 bits long, one per word. Every digit in the machine had one parity bit, for error checking, meaning every word occupied 60 bits (48 data with 12 parity check). The basic configuration had 26 general purpose registers and could be expanded to 99 general purpose registers. The general purpose registers had an access time of 1 microsecond.

The basic configuration had one Computer and could be expanded to a multiprocessor with a second Computer.

The Processor is an independent CPU (with a different instruction set from the Computers) and provides control for 12 to 24 Magnetic drum storage units, 4 to 40 UNISERVO II tape drives, 2 Electronic page recorders, 1 or 2 High-speed printers, and 0 or 1 High-speed punchcard reader.

The LARC used core memory banks of 2500 words each, housed 4 banks per memory cabinet. The basic configuration had 8 banks of core (2 cabinets), 20000 words. The memory could be expanded to a maximum of 39 banks of core (10 cabinets with one empty bank), 97500 words. The core memory had one parity bit on each digit, for error checking, resulting in 60 bits per memory word. The core memory had an access time of 8 microseconds and a cycle time of 4 microseconds. Each bank operated independently and could begin a new access in any 4 microsecond cycle when it was not already busy. By properly interleaving accesses to different banks the memory could sustain an effective access time of 4 microseconds on each access (e.g., instruction access in one bank data in another).

The data transfer bus connecting the two Computers and the Processor to the core memory was multiplexed to maximize throughput; every 4 microsecond bus cycle was divided into eight 500 nanosecond time slots:

1. Processor - instructions and data
2. Computer 1 - instructions
3. Computer 2 - data
4. I/O DMA Synchronizer - data
5. Not Used
6. Computer 2 - instructions
7. Computer 1 - data
8. I/O DMA Synchronizer - data

The core memory system enforces a system of interlocks and priorities to avoid simultaneous access of the same memory bank by multiple sections of the system (the Computers, Processor, and I/O DMA Synchronizers) without conflicts or deadlocks. A memory bank is unavailable for one 4 microsecond cycle after being addressed by any section of the system. If another section attempts to address the same memory bank during this time it is locked out and must wait then try again in the next 4 microsecond cycle. To prevent deadlocks and timeouts in the I/O system the following priorities are enforced:

1. I/O DMA Synchronizer - Highest
2. Processor
3. Computers - Lowest

If a higher priority section is locked out in one 4 microsecond cycle, when it trys again in the next 4 microsecond cycle, all lower priority sections are prevented from beginning a new cycle on that memory bank until the higher priority section has completed its access.

External links

• Universal Automatic Computer Model LARC (http://ed-thelen.org/comp-hist/BRL61-u3.html)
• LARC Manuals and documentation (http://www.bitsavers.org/pdf/univac/larc/)