Dynamic random access memory
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DRAM is a type of random access memory that stores each bit of data in a separate capacitor. The number of electrons stored in the capacitor determines whether the bit is considered 1 or 0. As the capacitor leaks electrons, the information gets lost eventually, unless the charge is refreshed periodically. Because it must be refreshed periodically, it is a dynamic memory as opposed to SRAM and other static memory. Also, since DRAM loses its data when the power supply is removed, it is in the class of volatile memory devices. DRAM is also in the class of solid-state memory.
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Missing image Square_array_of_mosfet_cells_read.png Principle of operation of DRAM read, for simple 4 by 4 array. |
Missing image Square_array_of_mosfet_cells_write.png Principle of operation of DRAM write, for simple 4 by 4 array. |
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Principle of operation of DRAM
DRAM is usually arranged in a square array of capacitors, as shown in the illustrations here which show a simple example with only 4 by 4 cells (more typical DRAM has 1024 by 1024 cells). During a read of any cell, the entire row is read out and written back in (refresh). During a write to a particular cell, the entire row is read out, one value changed, and then the entire row is written back in, as illustrated in the figure to the right.
DRAM cells are smaller and therefore cheaper than SRAM cells, which operate by flip-flops rather than capacitors (1 transistor and 1 capacitor take less space than 6 transistors).
Typically, manufacturers specify that each row should be refreshed every 64 ms or less. Refresh logic is commonly used with DRAMs to automate the periodic refresh. This makes the circuit more complicated, but this drawback is usually outweighed by the fact that DRAM is so much cheaper than SRAM. Some systems refresh every row in a tight loop that occurs once every 64 ms. Other systems refresh one row at a time -- for example, a system with 2^13 = 8192 rows would have a refresh rate of one row every 64 ms / 8192 = 7.8 µs. Both methods require some sort of counter to keep track of which row is the next to be refreshed. Some DRAM chips include that counter; other kinds require external refresh logic to hold that counter. (Under some conditions, most of the data in DRAM can be recovered even if the DRAM has not been refreshed for several minutes [1] (http://parts.jpl.nasa.gov/docs/DRAM_Indiv-00.pdf).)
Another alternative to DRAM is Flash memory. Currently available flash memory is slightly cheaper per bit than DRAM, is non-volatile, but is much slower than DRAM when reading (and much, much, much slower than DRAM when writing), and will eventually wear out after several thousand write cycles.
It is possible that electrical or magnetic interference inside a computer system could cause a single bit of DRAM spontaneously flip to the opposite state. Some research has shown that the majority of one-off ("soft") errors in DRAM chips occur as a result of cosmic rays, which may change the contents of one or more memory cells, or interfere with the circuitry used to read/write them - there is some concern that as DRAM density increases further, and thus the components on DRAM chips get smaller, whilst at the same time operating voltages continue to fall, DRAM chips will be affected by such radiation more frequently - since lower energy particles will be able to change a memory cell's state. On the other hand, smaller cells make smaller targets, and moves to technologies such as SOI may make individual cells less susceptible and so counteract, or even reverse this trend.
You can hide from cosmic rays by putting a lot of dense, heavy stuff (e.g. lead, concrete, or rock between your computer and the rest of the universe - the atmosphere also stops a lot - equivalent to about 4 meters of concrete at sea level, but noticeably less at higher altitudes (soft errors have been quoted as being 100x to 600x more common in a plane at 35,000 feet, than they are at sea level). At the moment (2005), this happens so rarely that it is not worth worrying about for most home users.
Some systems require high reliability (e.g. servers), or are in high-radiation environments where this happens more often (e.g. satellites). Those systems deal with this problem by using special DRAM modules that include extra memory bits - ECC-capable memory controllers can then use error detection functions to detect when it happens, and possibly ECC functions to narrow down exactly which bit was in error and correct it. Error-correction functions in PCs can typically detect, and correct errors of a single bit per 64 bit word, and detect (but not correct) errors of two, or more bits per 64 bit word.
DRAM Interface
An important feature of DRAMs is called address multiplexing. This technique splits the address in half and feeds each half in turn to the chip on the same set of pins. Many microprocessors include control logic for DRAMs, relieving the circuit designer from the need to provide address multiplexing logic.
The chip has a large array of memory capacitors that are arranged in rows and columns. To read one location in the array, the control circuit first calculates its row number, which it places on the DRAM's address pins. It then toggles the row address select (RAS) pin, causing the DRAM to read the row address. Internally, the DRAM connects the selected row to a bank of amplifiers called sense amplifiers, which read the contents of all the capacitors in the row. The control circuit then places the column number of the desired location on the same address pins, and toggles the column address select (CAS) pin, causing the DRAM to read the column address. The DRAM uses this to select the output of the sense amplifier corresponding to the selected column. After a delay called the CAS access time, this output is presented to the outside world on the DRAM's data I/O pin.
To write data to the DRAM, the control logic uses the same two-step addressing method, but instead of reading the data from the chip at the end of the operation, it provides data to the chip at the start of the operation.
After a read or write operation, the control circuit returns the RAS and CAS pins to their original states to ready the DRAM for its next operation. The DRAM requires a certain interval called the precharge interval between operations.
Once the control circuit has selected a particular row, it can select several columns in succession by placing different column addresses on the address pins, toggling CAS each time, while the DRAM keeps the same row activated. This is quicker than accessing each location using the full row-column procedure. This method is useful for retrieving microprocessor instructions, which tend to be stored at successive addresses in memory.
The above description is for a one-bit DRAM. Many DRAMs are multibit devices (often four or eight bits), having a number of storage arrays operating simultaneously. Each array is attached to its own data I/O pin, allowing multiple bits of data to be transferred on each read or write. This is logically equivalent to having multiple one-bit DRAMs operating in tandem, but uses less space since all the arrays share the same address and control pins.
Special Types of DRAM
Fast page mode DRAM
Fast page mode DRAM is also called FPM DRAM, Page mode DRAM, Fast page mode memory, or Page mode memory.
In page mode, a row of the DRAM can be kept "open", so that successive reads or writes within the row do not suffer the delay of precharge and accessing the row. This increases the performance of the system when reading or writing bursts of data.
Static column is a variant of page mode in which the column address does not need to be strobed in.
Nibble mode is another variant in which four sequential locations within the row can be accessed.
Extended data out (EDO) DRAM
EDO DRAM is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. This allows a certain amount of overlap in operation (pipelining), allowing somewhat improved speed. It was 5% faster than Fast Page Mode DRAM, which it began to replace in 1993.
Burst EDO (BEDO) DRAM
An evolution of the former, Burst EDO DRAM, could process four memory addresses in one burst, for a maximum of 5-1-1-1, saving an additional three clocks over optimally designed EDO memory. It was done by adding an address counter on the chip to keep track of the next address. BEDO also added a pipelined stage allowing page-access cycle to be divided into two components. During a memory-read operation, the first component accessed the data from the memory array to the output stage (second latch). The second component drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, faster access time is achieved (up to 50% for large blocks of data) than with traditional EDO.
Although BEDO DRAM showed additional optimization over EDO, by the time it was available, the market had made a significant investment towards synchronous DRAM, or SDRAM [2] (http://www6.tomshardware.com/motherboard/19981024/ram-06.html).
Synchronous Dynamic RAM (SDRAM)
SDRAM is an improved type of DRAM. Whilst DRAM has an asynchronous interface, meaning that it reacts immediately to changes in its control inputs, SDRAM has a synchronous interface, meaning that it waits for a clock pulse before responding to its control inputs. The clock is used to drive an internal finite state machine that can pipeline incoming commands. This allows the chip to have a more complex pattern of operation than plain DRAM.
Pipelining means that the chip can accept a new command before it has finished processing the previous one. In a pipelined write, the write command can be immediately followed by another command without waiting for the data to be written to the memory array. In a pipelined read, the requested data appears a fixed number of clock pulses after the read command. It is not necessary to wait for the data to appear before sending the next command. This delay is called the latency, and is an important parameter to be considered when purchasing SDRAM for your computer.
SDRAM was introduced in 1997, and by the 2000s had replaced plain DRAM in modern computers, because of its greater speed.
Double data rate (DDR) SDRAM
Double data rate (DDR) SDRAM is a later development of SDRAM, used in PC memory from 2000 onwards. All types of SDRAM use a clock signal that is a square wave. This means that the clock alternates regularly between one voltage (low) and another (high), usually millions of times per second. Plain SDRAM, like most synchronous logic circuits, acts on the low-to-high transition of the clock and ignores the opposite transition. DDR SDRAM acts on both transitions, thereby halving the required clock rate for a given data transfer rate.
The DDR SDRAM standard is evolving, from DDR to DDR2 to DDR-3. At the time of writing (December 2004), DDR is still the main memory standard, but DDR2 is now supported by some chipsets and is beginning initial adoption. DDR2 is expected to become the major standard in 2005, while DDR-3 is under development and standardization within JEDEC has started. The difference between DDR, DDR2, DDR-3 is mostly in differing supply voltages, different speed classes, as well as some changes in the exact specification of the interface.
- DDR: supply voltage VDD = 2.5 V
- DDR2: supply voltage VDD = 1.8 V
- DDR-3: supply voltage VDD not yet standardized (draft specifications call for 1.2 to 1.6 V)
Direct Rambus DRAM (DRDRAM)
Direct Rambus DRAM (DRDRAM), often called RDRAM, is internally similar to DDR SDRAM, but uses a special method of signaling developed by the Rambus Company that allows faster clock speeds. RDRAM chips are packaged on modules called RIMMs, which are not compatible with the DIMMs used for plain SDRAM. Intel licensed the Rambus technology and introduced chipsets with RDRAM support. Early P4 systems could only use RDRAM, but as prices remained high, Intel finally introduced support for DDR. (The company VIA had a DDR chipset for the Pentium 4 before this, but legal threats put motherboard manufactures off using it. VIA then decided to make their own boards with the chipset but theese didn't gain much traction either) RDRAM all but disappeared in new systems around 2003, due to the availibility of DDR chipsets for the Pentium 4 and the lower cost of SDRAM. Sony used RDRAM in its PlayStation 2 video game console, and announced it would use Rambus's XDR memory in its PlayStation 3, expected in 2006.
Video DRAM (VRAM)
VRAM is a dual-ported version of DRAM formerly used in graphics adaptors. It is now almost obsolete, having been superseded by SDRAM and SGRAM. VRAM has two paths (or ports) to its memory array that can be used simultaneously. The first port, the DRAM port, is accessed as with plain DRAM. The second port, the video port, is read-only, and is dedicated to feeding a fast stream of data to the display. To use the video port, the controller first uses the DRAM port to select the row of the memory array that is to be displayed. The VRAM then copies that entire row to an internal shift-register. The controller can then continue to use the DRAM port for drawing objects on the display. Meanwhile, the controller feeds a clock called the shift clock (SCLK) to the VRAM's video port. Each SCLK pulse causes the VRAM to deliver the next item of data, in strict address order, from the shift-register to the video port. For simplicity, the graphics adaptor is usually designed so that the contents of a row, and therefore the contents of the shift-register, corresponds to a complete horizontal line on the display.
Synchronous graphics RAM (SGRAM)
SGRAM is a specialized form of SDRAM for graphics adaptors. It adds functions such as bit masking (writing to a specified bit plane without affecting the others) and block write (filling a block of memory with a single colour).
Pseudostatic RAM (PSRAM)
PSRAM is dynamic RAM with built-in refresh and address-control circuitry to make it behave similarly to static RAM (SRAM). It combines the high density of DRAM with the ease of use of true SRAM.
Some DRAM can switch between "self-refresh mode" and normal external-refresh mode [3] (http://www.palmgaulois.com/faql06.html)[4] (http://www.epinions.com/cmd-review-4D86-3C78BB9-39711BE0-prod1).
External links
- Basic DRAM operation (http://www.cs.berkeley.edu/~pattrsn/294/LEC9/lec.html) has some interesting historical trend charts of cell size and DRAM density -- but they only go to 1995. Anyone have more recent data?
- Back to Basics - Memory, part 3 (http://www.computerwriter.com/archives/1998/cw052198.htm)
- Benefits of Chipkill-Correct ECC for PC Server Main Memory (http://www-1.ibm.com/servers/eserver/pseries/campaigns/chipkill.pdf) - A 1997 discussion of SDRAM reliability - some interesting information on "soft errors" from cosmic rays, especially with respect to Error-correcting_code schemes
- Soft errors' impact on system reliability (http://www.edn.com/article/CA454636.html) - Ritesh Mastipuram and Edwin C Wee, Cypress Semiconductor, 2004
- Scaling and Technology Issues for Soft Error Rates (http://www.nepp.nasa.gov/DocUploads/40D7D6C9-D5AA-40FC-829DC2F6A71B02E9/Scal-00.pdf) - A Johnston - 4th Annual Research Conference on Reliability Stanford University, October 2000
- Challenges and future directions for the scaling of dynamic random-access memory (DRAM) (http://www.research.ibm.com/journal/rd/462/mandelman.html) - J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. DeBrosse, R. Divakaruni, Y. Li, and C. J. Radens, IBM 2002de:Dynamisches RAM
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