Field-programmable gate array

A field-programmable gate array or FPGA is a semiconductor device used to process digital information, similar to a microprocessor. It utilizes gate array technology that can be reprogrammed after it is manufactured, rather than having its programming fixed during the manufacturing — a programmable logic device.

FPGAs are generally slower than their Application-specific integrated circuit (ASIC) counterparts, and draw more power. However, they have several advantages such as a shorter time-to-market, and lower development costs (for quantities fewer than 10k). Certain FPGA vendors offer an ASIC made as a so-called hard copy of an FPGA — that is, an integrated circuit with the same functionality as the FPGA, but faster and consuming less power.

Many modern FPGAs have the ability to be reprogrammed at "run time", and this is leading to the idea of reconfigurable computing or reconfigurable systems — CPUs that reconfigure themselves to suit the task at hand. Software-configurable microprocessors such as the Stretch S5000 adopt a hybrid approach by providing a processor core and an FPGA core on the same chip.

Contents

1 Applications 2 Architecture 3 FPGA Design and programming 4 Basic process technology types 5 FPGA manufacturers 6 FPGA Research 7 See also 8 External links 8.1 FPGA manufacturers

Applications

Applications of FPGAs include DSP, Software-defined radio, Aerospace and defense systems, ASIC Prototyping, Medical imaging, Computer vision, Speech recognition, Cryptography, Bioinformatics, and a growing range of other areas.

Architecture

The architecture consists of an array of logic blocks and routing channels. Two I/O pads fit into the height of one row or the width of one column. All the routing channels have the same width (number of wires).

Each circuit must be mapped into the smallest square FPGA that can accommodate it. For example, a circuit containing 14 logic blocks and 10 I/O pads would be mapped into an FPGA consisting of a 4x4 array of logic blocks.

The FPGA logic block consists of a 4-input lookup table (LUT), and a flip-flop, as shown at below.

There is only one output, which can be either the registered or the unregistered LUT output. The logic block has four inputs for the LUT and a clock input. Since the clock is normally routed via a special-purpose dedicated routing network in commercial FPGAs, do NOT route it or include it in your track count results. That is, you can completely ignore the clock net, since it is assumed to be routed on a special global network. In their Stratix II FPGAs, FPGA vendor Altera has implemented a new type of LUT (utlizing up to 7 inputs) called the ALM (http://www.altera.com/products/devices/stratix2/features/architecture/st2-lut.html)

The locations of the FPGA logic block pins are shown below.

Each input is accessible from one side of the logic block, while the output pin can connect to routing wires in both the channel to the right and the channel below the logic block.

Each logic block output pin can connect to any of the wiring segments in the channels adjacent to it. The figure below should make the situation clear.

Similarly, an I/O pad can connect to any one of the wiring segments in the channel adjacent to it. For example, an I/O pad at the top of the chip can connect to any of the W wires (where W is the channel width) in the horizontal channel immediately below it.

The FPGA routing is unsegmented. That is, each wiring segment spans only one logic block before it terminates in a switch box. By turning on some of the programmable switches within a switch box, longer paths can be constructed.

Whenever a vertical and a horizontal channel intersect there is a switch box. In this architecture, when a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments. The pattern, or topology, of switches used in this architecture is the planar or domain-based switch box topology. In this switch box topology, a wire in track number one connects only to wires in track number one in adjacent channel segments, wires in track number 2 connect only to other wires in track number 2 and so on. The figure below illustrates the connections in a switch box.

FPGA Design and programming

To define the behaviour of the FPGA it is required to use a Hardware Description Language (HDL) or a schematic designed using an Electronic design automation tool. Either of these, when compiled, will generate a netlist, that can be mapped to the actual FPGA architecture. When done the binary file generated is used to (re)configure the FPGA device. Common HDLs are VHDL and Verilog.

To simplify the design there exist libraries of predefined complex functions and circuits, which have been tested and optimized to speed up the design process. Predefined circuits are commonly called intellectual property blocks.

Basic process technology types

• SRAM - based on static memory technology. In-system programmable and re-programmable. Requires external boot devices. Usually CMOS.
• Antifuse - One-time programmable. CMOS.
• EPROM - Eraseable Programmable Read-Only Memory technology. Usually one-time programmable in production because of plastic packaging. Windowed devices can be erased with ultraviolet (UV) light. CMOS.
• EEPROM - Electrically Eraseable Programmable Read-Only Memory technology. Can be erased, even in plastic packages. Some, but not all, EEPROM devices can be in-system programmed. CMOS.
• FLASH - Flash-erase EPROM technology. Can be erased, even in plastic packages. Some, but not all, FLASH devices can be in-system programmed. Usually, a FLASH cell is smaller than an equivalent EEPROM cell and is therefore less expensive to manufacture. CMOS.
• Fuse - One-time programmable. Bipolar.

FPGA manufacturers

Device manufacturers include Actel, Altera, Atmel, Cypress, Lattice Semiconductor, QuickLogic, ST Microelectronics, and Xilinx.

FPGA Research

• FPGA Research at the University of Toronto (http://www.eecg.toronto.edu/EECG/RESEARCH/FPGA.html)
• LCR (http://www.icmc.usp.br/~lcr/)
• FPGA Research Groups (http://www.emlabs.info/taxonomy/term/36) - a list of Universities and Research Groups that are engaged in FPGA developing.

See also

• CPLD

External links

• comp.arch.fpga (http://groups.google.com/groups?group=comp.arch.fpga) Google archive of Usenet groups, where people interested in FPGA hang out.
• FPGA Articles (http://www.dsp-fpga.com/articles/topics/FPGAs/) FPGA articles from DSP-FPGA.com
• Opencores (http://www.opencores.org) A set of free IP cores that can be implemented in FPGAs
• Comprehensive tutorial on FPGA (http://www.tutorial-reports.com/computer-science/fpga/)
• A comprehensive list of FPGA CPUs (http://www.fpgacpu.org/links.html)
• A good FPGA tools overview (http://www.rtcmagazine.com/home/article.php?id=100125)
• FPGAworld news, jobs, forums, demos etc. (http://www.fpgaworld.com)
• FPGA Basics by Ray Andraka (http://andraka.com/whatisan.htm)
• Fpga4Fun various fpga projects (http://www.fpga4fun.com)
• FPGA Boards (http://www.fpga-faq.com/FPGA_Boards.shtml)
• Information about signal processing on FPGA by RF Engines  (http://www.rfel.com/whipapdat.asp)

FPGA manufacturers

• Xilinx (http://www.xilinx.com/) Xilinx has traditionally been the FPGA leader. Their general philosophy is to provide all the features possible, at the cost of extra complexity.
• Altera (http://www.altera.com/) Altera is the second FPGA heavyweight. Their philosophy is to provide the features that most people want while keeping their devices easy to use.
• Lattice (http://www.latticesemi.com/products/fpga/index.cfm) Lattice's focus is on low-cost, feature-optimized FPGAs and non-volatile, flash-based FPGAs.
• Actel (http://www.actel.com/) has antifuse (programmable-only-once) products.
• QuickLogic (http://www.quicklogic.com/) has antifuse (programmable-only-once) products.
• Cypress (http://www.cypress.com/cypress/prodgate/prog.html)
• Atmel (http://www.atmel.com/)
• Debian FPGA (http://wiki.debian.net/?FPGA).

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